Mid Level ASIC Design Engineer

Job Title

Mid Level ASIC Design Engineer

Role Summary

Responsible for microarchitecture and implementation of high-performance AI inference ASICs. The role covers coupling accelerator compute, interconnects, CPU and third-party IP, and working across architecture, verification, and backend teams to meet performance, power, and timing targets.

This is an individual-contributor role on the ASIC team in a fast-paced startup environment.

Experience Level

Mid-level — requires 3+ years of ASIC design experience.

Responsibilities

Deliver microarchitecture and implementation tasks across front-end and interactions with backend and verification teams.

• Reconcile micro-architecture changes with system architecture and document decisions.
• Define and document microarchitecture for compute blocks and system interfaces.
• Select and integrate third-party IP blocks (including CPU IP) into SoC designs.
• Collaborate with design verification engineers to ensure correct RTL behavior.
• Run and analyze frontend synthesis; identify and resolve synthesis issues.
• Provide place-and-route guidance and support timing closure with backend teams.
• Leverage GenAI tools to improve workflows while maintaining ownership and quality of generated collateral.

Requirements

Core technical skills and practical ASIC design experience required for success in this role.

• 3+ years of ASIC design experience with RTL logic design in multi-million gate ASICs using Verilog or SystemVerilog.
• Experience integrating IP, specifically CPU IP into SoC environments.
• Knowledge of ARM, RISC-V or MIPS architectures; memory hierarchy, cache coherency, virtual memory, and multicore CPU operation.
• Familiarity with AMBA/APB/AXI protocols and common peripheral interfaces (SPI, eMMC, MII, GPIO, I2C).
• Hands-on experience with front-end tools and ASIC development methodologies.
• Familiarity with low-power design flows and UPF for multiple power domains.
• Self-starter capable of working in a dynamic startup environment.

• Previous experience with timing closure at high frequencies.
• Interest or experience exploring AI architectures (convolution, transformer, etc.).

Education Requirements

Bachelor of Science in Electrical Engineering or Computer Engineering required. Master of Science preferred.

About the Company

Company: Tensordyne

Tensordyne is a startup developing high-performance, low-power AI inference processors and multi-chip systems for generative AI acceleration in data centers. The company focuses on ASIC design, verification, and integration of computational accelerators with third-party SoC IP.