Mid-End ASIC Engineer, Senior

Job Title

Mid-End ASIC Engineer, Senior

Role Summary

Hands-on senior engineer responsible for synthesis, timing convergence, and logical design quality for an AI accelerator roadmap. Works within the implementation team and coordinates with architecture, RTL, backend, and external partners to deliver implementation-ready netlists and meet timing signoff criteria.

Experience Level

Senior — the role expects extensive experience; the posting specifies 12+ years of ASIC implementation experience with successful tapeouts.

Responsibilities

Primary responsibilities include defining methodology, executing synthesis and timing closure, and leading cross-functional technical execution.

• Define and own synthesis methodology for current and future ASIC generations.
• Establish signoff criteria for synthesis deliverables and ensure quality of results (QoR).
• Perform hands-on synthesis using tools such as Cadence Genus and/or Synopsys Design Compiler.
• Develop and maintain SDC constraints and timing budgets; drive logical timing closure and optimization.
• Perform root-cause analysis of timing bottlenecks and implement fixes with RTL and physical-aware optimizations.
• Collaborate with architecture, RTL, and backend teams to mitigate timing risks and align on budgets.
• Lead cross-functional issue resolution and act as the synthesis technical lead with external partners, reviewing QoR and timing reports.
• Apply AI techniques to improve timing analysis and automation where applicable.

Requirements

Must-have technical skills and experience; concise listing of required and desirable qualifications.

• Must-have: 12+ years of ASIC implementation experience with successful tapeouts.
• Must-have: Proven expertise in synthesis methodology and flow development.
• Must-have: Deep knowledge of timing closure for complex designs and strong SDC/constraint development skills.
• Must-have: Proficiency with Cadence Genus and/or Synopsys Design Compiler.
• Must-have: Strong RTL design understanding and implementation-friendly practices.
• Must-have: Hands-on experience with advanced process nodes (5nm and below).
• Must-have: Strong Tcl and Python scripting skills for automation and analysis.
• Must-have: Excellent debugging and root-cause analysis capabilities; strong cross-functional collaboration skills.
• Nice-to-have: Experience applying AI/ML techniques to timing analysis or engineering automation; prior leadership coordinating with external partners.

Education Requirements

Not specified.

About the Company

Company: Positron AI

Positron AI designs custom hardware systems and SoC solutions to accelerate AI inference, focusing on high-performance, energy-efficient alternatives to traditional GPU-based inference platforms.