Memory Yield Engineer, Staff

Job Title

Memory Yield Engineer, Staff

Role Summary

Lead yield optimization for advanced 3D SoC + memory products by driving memory test, wafer/package yield analysis, and process monitoring. Act as the engineering interface between Qualcomm and memory suppliers to ensure product requirements and qualification targets are met.

Own root-cause investigations, corrective actions across fab/test/design, and post-qualification tuning to improve production yields and reliability.

Experience Level

Senior — staff-level role. Recommended 7+ years of experience in DRAM test and wafer yield analysis and improvement engineering; experience leading supplier engagements and cross-functional teams.

Responsibilities

Primary responsibilities include:

• Monitor fab in-line, wafer acceptance test (WAT) and measurement data to ensure process stability and spec compliance.
• Perform statistical wafer- and package-level test data analysis; apply and evaluate memory repair schemes.
• Conduct root-cause failure analysis using process history and test results; correlate failures to fab/process/test/design sources.
• Drive corrective actions across fab processes, wafer test, package test, and design to address yield loss.
• Support failure analysis during SOC+memory system-level characterization and reliability qualification tests.
• Coordinate test flow, hardware setup, and integration between Qualcomm, fabs, test teams, and memory suppliers.
• Lead post-qualification yield improvement activities and support analysis of customer return samples.

Requirements

Must-have skills and experience:

• Minimum 7+ years in DRAM test and wafer yield analysis and improvement engineering.
• Strong knowledge of DRAM test methodologies, fab defect control, in-line/WAT/AC/DC measurement data analysis, and failure analysis techniques.
• Experience with DRAM product qualification and repair schemes for yield improvement.
• Ability to define test coverage, fab process monitoring specifications, and wafer/package-level test conditions for mature yield targets.
• Familiarity with DRAM package-level test, memory process integration, basic device physics, design verification, and test patterns.
• Proven ability to lead supplier engagements, multitask, and coordinate cross-functional corrective actions.
• Excellent written and verbal English communication skills and strong interpersonal/teamwork skills.
• Willingness to travel occasionally to supplier sites.

Nice-to-have:

• Experience as a DRAM product engineer.
• Flash memory yield improvement experience.
• Broader knowledge of device physics, 3D wafer bonding, and test flow optimization to reduce field memory failures.

Education Requirements

Bachelor's degree in Electrical Engineering or equivalent engineering discipline is required; Master’s or PhD in Electrical Engineering is preferred. The posting also lists alternative minimum qualification combinations for related ASIC roles: Bachelor's + 4+ years, Master's + 3+ years, or PhD + 2+ years of relevant experience in science or engineering.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.