Memory System Designer and Place and Route Engineer

Job Title

Memory System Designer and Place and Route Engineer

Role Summary

Design engineer on the Central Engineering memory subsystem team responsible for architecting and delivering large memory blocks and subsystems. Work spans RTL implementation, synthesis, place-and-route, and physical design closure.

Experience Level

Senior - typically requires a minimum of 8 years of relevant experience.

Responsibilities

Primary responsibilities include:

• Architect and design memory subsystems.
• Implement and debug Verilog RTL for subsystems.
• Perform place-and-route and physical implementation.
• Drive design closure: timing, DRC, LVS, EM/IR.
• Run gate-level netlist synthesis and related flows.
• Run and debug logical equivalency checks and static timing analysis.
• Develop automation scripts and tooling to support flows.

Requirements

Must-have technical skills and experience:

• Strong digital design skills and familiarity with memory behavior.
• Proficient in Verilog RTL coding and debugging.
• Place-and-route and physical-design expertise.
• Experience with STA, DRC, EM/IR, and achieving design closure.
• Familiarity with synthesis tools and gate-level synthesis flows.
• Ability to code in Python and write automation scripts.
• Experience with logical equivalency checking tools.
• Good communication and leadership abilities; self-driven and able to multitask.

Nice-to-have:

• Prior experience with large memory block or subsystem design.

Education Requirements

Bachelor's degree in Electrical Engineering is required (or equivalent practical experience as stated in the posting).

About the Company

Company: Broadcom

Headquarters: Irvine, California, United States

Broadcom is a global technology leader that designs, develops, and supplies a wide range of semiconductor and infrastructure software solutions. The company is known for its innovations in wireless and broadband communications, enabling a connected world.