Memory Subsystem Engineer, MLA Technology

Job Title

Memory Subsystem Engineer, MLA Technology

Role Summary

Design, validate, and operate memory subsystems for next-generation machine learning silicon and servers at Annapurna Labs (AWS). The team works across HBM, SRAM, UCIe, and chiplet interconnects and spans hardware, firmware, and software engineering, supporting manufacturing and data center deployments.

Experience Level

Mid-level (Level - Mid-Career). Role expects at least 5 years of practical semiconductor design experience and carries senior responsibilities for subsystem integration and cross-functional debug.

Responsibilities

Primary responsibilities include design, integration, validation, and operational support of memory subsystems:

• Collaborate with architects, ASIC design teams, and software engineers on ML chip and server integration.
• Support debug and operations of deployed ML chips in manufacturing and data center environments.
• Integrate IP, support packaging and silicon bring-up, perform characterization and validation of memory subsystems.
• Develop and maintain scripts and test automation (lua, bash, python, etc.) to execute validation and operational tasks at scale.
• Drive cross-functional triage for functional and performance issues and lead root-cause analysis through bring-up to production.
• Collect and analyze large-scale fleet and manufacturing data to identify reliability and performance improvements.
• Mentor teammates, participate in design reviews, and contribute to hiring and team skill development.

Requirements

Must-have technical qualifications and desirable experience:

• Must-have: 5+ years practical semiconductor design experience, including full-chip and subsystem integration.
• Must-have: Strong understanding of memory training, timing parameters, and controller features.
• Must-have: Ability to write and maintain scripts/tools (lua, bash, python, etc.).
• Must-have: Knowledge of DDR, HBM, and UCIe PHY and controller protocols.
• Must-have: Experience collaborating with vendors, physical-design teams, manufacturing, and data-center operators to debug and resolve issues.
• Nice-to-have: 3+ years SOC/IO/subsystem experience and close work with physical design to optimize power, performance, and area.
• Nice-to-have: Experience with IP integration, 2.5D packaging, clocking and timing constraints, SERDES, and high-speed analog technologies.
• Nice-to-have: Proven system-level debug through bring-up, characterization, validation, and production phases.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Systems Engineering, or a closely related field (as stated in the posting).

About the Company

Company: Amazon

Headquarters: Seattle, Washington, United States

Amazon is a global leader in e-commerce and cloud computing, committed to delivering fast, reliable services across diverse sectors. The company's innovative technologies include AWS, Kindle, and Echo, as well as developing low Earth orbit satellite networks for improved internet connectivity worldwide.