Memory Mask Design Engineer

Job Title

Memory Mask Design Engineer

Role Summary

Work in the Full Custom Memory layout group to implement IC layout for high-performance, high-speed digital memory circuits in advanced CMOS foundry nodes. The role focuses on full-custom memory IP layout, floorplanning, block routing and top-level verification to meet performance and manufacturability targets.

Team mission: deliver robust, manufacturable memory layouts for advanced process nodes used in NVIDIA products.

Experience Level

Mid-level — requires approximately 2+ years of relevant industry experience in memory layout or equivalent.

Responsibilities

Primary responsibilities include executing full-custom memory layout and ensuring layout quality and manufacturability.

• Implement full-custom IC layouts for digital memory circuits in advanced CMOS nodes (3nm/5nm/7nm and below).
• Develop layouts for memory IP containing significant digital components.
• Adopt and apply best practices and layout methodologies for composing memory arrays and macros.
• Perform floor planning, block-level routing, and macro-level assembly.
• Follow company procedures for layout activities and collaborate with verification and design teams.

Requirements

Must-have technical skills and experience.

• 2+ years of hands-on experience in memory layout for advanced CMOS processes (experience requirement noted in Education section).
• Proficient with industry-standard EDA tools, especially Cadence layout toolflows.
• Experience with layout of high-performance memories (various memory types and bitcell architectures).
• Knowledge of layout fundamentals: matching devices, symmetrical layout, signal shielding, and common memory block elements (decoders, IO, etc.).
• Experience with floorplanning, block-level routing, macro assembly, and top-level integration.
• Familiarity with top-level verification and EM/IR quality checks; understanding of layout-dependent effects including LOD, dummification, and fill strategies.
• Ability to follow established procedures and contribute to layout methodology improvements.

Education Requirements

B.E./B.Tech. or M.Tech. in Electronics (or equivalent practical experience). The posting also accepts equivalent experience in lieu of degree. The role expects approximately 2+ years of proven experience in memory layout in advanced CMOS processes.

About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.