Memory Layout Manager

Job Title

Memory Layout Manager

Role Summary

Lead a team of layout engineers to deliver SRAM, RF, ROM, and CAM memory compiler layouts for advanced FinFET and GAA process technologies. Own technical execution, cross-functional coordination with circuit design, tilers, and foundry partners, and the advancement of layout methodology and automation.

Primary focus areas include floorplanning, high-density placement and routing, physical sign-off (DRC, LVS, extraction), yield and reliability (EM, IR), and applying AI/ML to improve automation and design quality.

Experience Level

Senior level - requires 15+ years of relevant experience in memory compiler layout design and management.

Responsibilities

Manage team delivery, technical direction, and cross-functional integration for memory compiler layout projects.

• Lead and mentor layout engineers to develop memory compiler designs for FinFET and GAA nodes.
• Oversee design, modification, analysis, and verification of memory layouts and compilers.
• Define and enforce layout methodologies for analog, digital, memory, and standard cells.
• Manage physical sign-off flows including DRC, LVS, parasitic extraction, DFM, and yield analysis.
• Optimize area, performance, power, and manufacturability through floorplanning and placement/routing templates.
• Develop and integrate automation using SKILL, Python, or Tcl and apply AI/ML techniques to accelerate routing, placement, and DRC debugging.
• Coordinate with circuit design, tilers, and foundry teams to meet tape-out and quality targets.
• Plan resources, track project progress, and maintain accountability for deliverables and schedules.

Requirements

Key technical and leadership qualifications.

• 15+ years of hands-on experience in memory compiler layout design and technical leadership.
• Proven tape-out experience on advanced foundry geometries (for example 3nm, 2nm or below).
• Expert-level proficiency with EDA tools such as Cadence Virtuoso, Siemens Calibre, and Synopsys IC Validator.
• Deep knowledge of layout methodologies, floorplanning, placement/routing strategies, and physical verification flows.
• Experience addressing yield, DFM, parasitic extraction, and reliability concerns (EM, IR, noise).
• Practical experience building automation flows using SKILL, Python, or Tcl; familiarity with AI/ML-driven EDA approaches is required.
• Demonstrated ability to lead engineering teams, manage complex projects, and communicate effectively across disciplines.
• Preferred: experience in strategic decision-making, performance management, and mentoring senior/staff engineers.

Education Requirements

Bachelor's or Master's degree in Electronics, Electrical, or VLSI Engineering is required.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.