Memory Layout Lead

Job Title

Memory Layout Lead

Role Summary

Lead and execute hands-on physical layout for advanced memory IP, managing a small team to deliver manufacturable, high-performance layouts. Coordinate with design, physical design, CAD, and project management to meet tape-out milestones and quality targets.

Experience Level

Senior-level. The role expects approximately 7–12+ years of layout experience.

Responsibilities

Accountable for technical delivery, team guidance, and cross-functional alignment for memory IP layout work.

• Lead hands-on layout design: floorplanning, placement, routing, and verification for memory IP blocks.
• Troubleshoot complex layout issues and perform root-cause analysis.
• Develop and maintain automation flows and scripts to improve productivity and quality.
• Ensure compliance with design rules, DRC/LVS checks, parasitic extraction, and foundry requirements.
• Review and approve critical layout blocks for performance, area, and manufacturability.
• Mentor and train layout engineers on advanced methodologies and best practices.
• Collaborate with memory design leads, physical design, CAD teams, and project managers on feasibility, estimates, and schedules.
• Present technical findings, risks, and mitigation plans to stakeholders.
• Support tape-out activities including final signoff and documentation.

Requirements

Must-have technical skills and work conditions.

• Proven experience leading layout teams and delivering layout projects.
• Strong understanding of layout tools, flows, and physical design constraints.
• Proficient with layout verification tools such as Calibre, ICV, and StarRC.
• Proficient with layout capture tools (Cadence Virtuoso or equivalent).
• Familiarity with advanced process nodes (example: 5nm, 3nm) and node-specific layout challenges.
• Experience developing or using automation flows and scripting to speed layout and checks.
• Knowledge of DRC/LVS processes and foundry signoff requirements.
• Excellent communication and organizational skills; ability to work in English with overseas teams.
• Work arrangement: 100% on-site in Da Nang, Vietnam.
• Preferred: domain experience in memory IP or custom analog/mixed-signal layout.

Education Requirements

B.S. or M.S. in Electrical Engineering or a related field.

About the Company

Company: Mixel