Memory Layout Design Engineer, Staff

Job Title

Memory Layout Design Engineer, Staff

Role Summary

Design and own custom memory layouts (SRAM, register files, ROM, memory compiler blocks) from floorplan through final signoff. Work with circuit designers, methodology and CAD teams to ensure manufacturable layouts that meet area, performance, power, and reliability targets across process nodes.

Drive DRC/LVS closure, technology migrations, and layout automation while mentoring junior designers and improving layout methodology.

Experience Level

Senior — guidance: 8 to 10 years of hands-on custom memory layout experience.

Responsibilities

Primary responsibilities include end-to-end memory layout design, verification, and methodology development.

• Design custom layouts for SRAM, register files, ROM, and memory compiler IP from floorplan to final signoff.
• Execute and resolve DRC, LVS, ERC, antenna, density, and reliability checks with Virtuoso and physical verification tools.
• Drive technology node migrations and resolve layout/verification issues introduced by new process rules.
• Collaborate with circuit designers to preserve schematic-layout correlation, device matching, and design intent.
• Develop and improve layout methodologies and automation scripts (Tcl, Perl, Python).
• Review and mentor junior engineers on complex layout challenges and best practices.
• Support customer-specific memory customization and deliver production-ready IP.

Requirements

Must-have technical skills and abilities; nice-to-have items listed where appropriate.

• Hands-on expertise in custom memory layout (SRAM, register files, ROM, memory compilers).
• Strong proficiency with Cadence Virtuoso or equivalent custom-layout platforms.
• Proven ability to close DRC/LVS issues, handle device matching and symmetry, and apply analog/custom layout techniques.
• Deep understanding of CMOS layout fundamentals, memory architecture, and FinFET technology challenges.
• Experience with parasitic extraction and physical verification flows and interpreting results.
• Familiarity with scripting for layout automation (Tcl, Perl, Python) is a strong plus.
• Ability to debug complex LVS mismatches and communicate layout trade-offs to circuit designers and teams.

Education Requirements

Bachelor's or Master's degree in Electronics, VLSI, Microelectronics, or a related technical field.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.