Memory Electrical Validation Engineer

Job Title

Memory Electrical Validation Engineer

Role Summary

Responsible for electrical validation of memory I/O interfaces and mixed-signal memory architectures to ensure product electrical performance, signal integrity, and production margins. Works within a hardware validation team collaborating with architecture, design, firmware, and presilicon verification teams.

This role contributes to product quality and yield by defining validation strategies, debugging electrical failures, and optimizing memory training and MRC at system level.

Experience Level

Mid-level — typically requires 5+ years of relevant experience in memory/DDR technology, system-level validation and debug.

Responsibilities

Key responsibilities include validating memory electrical performance, developing validation infrastructure, and driving resolution of electrical issues.

• Define electrical validation strategy for memory I/O to meet product and production targets.
• Validate analog circuit performance, signal integrity, and system-level margin against standards (e.g., JEDEC).
• Define and validate Memory Reference Code (MRC) requirements; analyze and optimize MRC steps and values.
• Develop validation procedures, analysis methods, and test infrastructure for margin validation.
• Debug and root-cause functional and electrical failures; coordinate fix and closure of test escapes and customer returns.
• Test interactions among electrical design features using validation infrastructure and lab equipment.
• Collaborate with architecture, design, and presilicon verification on DFT/DFM and IO architecture validation capabilities.
• Prepare validation specifications, evaluate IP, and generate test reports to ensure conformance to specifications.

Requirements

Must-have technical qualifications and experience; preferred items are listed separately.

Must-have:

• 5+ years experience in Memory/DDR technology.
• 5+ years hands-on system-level validation and debug of memory interfaces.
• 5+ years working with industry-standard JEDEC memory protocols and test methodologies.
• Hands-on validation & debug experience with lab equipment (oscilloscopes, signal generators, BERTs, logic analyzers).
• Ability to perform independent evaluation and selection of components and equipment based on specs and reliability.
• Regular onsite presence is required to fulfill essential job responsibilities.

Nice-to-have:

• Understanding of platform-level signal integrity and power integrity.
• Experience validating high-speed I/O: Tx/Rx, PLL/DLL, clocking, and equalization.
• Knowledge of CPU and DDR memory controller architectures and firmware/bios debug.
• Familiarity with Server/Xeon Memory RAS features and DDR training algorithms (MRC).
• Python scripting/programming for automation and analysis.
• Working knowledge of high-speed analog and digital IO circuits.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Physics, Computer Engineering, or a related technical field — or equivalent practical experience obtained through a combination of degree, research, prior jobs, or internships.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.