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Memory Circuit Design Engineer

Intel Corporation
June 23, 2026
Full-time
Remote friendly (Hillsboro, Oregon, United States)
Worldwide
$122,440 - $232,190 USD yearly
Semiconductor IP Jobs, Level - Mid-Career

Job Title

Memory Circuit Design Engineer

Role Summary

Join Intel's Advanced Design (AD) team within the Design Technology Platform to develop and deliver advanced embedded memory circuits and IP for Intel's CMOS process technologies. The role focuses on memory pathfinding, circuit innovation, layout automation, and enabling product designs that meet power, performance, and area goals.

Experience Level

Mid-level (Experienced hire). Typical expectation: Master's degree plus 4+ years of professional experience, or a PhD.

Responsibilities

Primary responsibilities include design and optimization of memory circuits, layout and automation, verification and validation, and cross-team collaboration to enable product integration.

  • Perform memory pathfinding and optimize power, performance, and area (PPA) through DTCO and design trade-offs.
  • Design, simulate, characterize, and verify custom memory circuits (SRAM, register files, ROM) and memory arrays/IP.
  • Develop memory bit-cell and complex periphery IC layout and layout automation.
  • Design test chips and drive memory circuit innovation for product enablement.
  • Execute pre-silicon verification and support post-silicon validation, debugging, yield and parametric tracking.
  • Collaborate with EDA vendors, process engineers, and product design teams to deliver design technology collateral and enablement.

Requirements

Must-have technical skills and experience. Preferred items are listed separately.

  • Experience designing, characterizing, and verifying custom memory circuits (SRAM, register files, ROM).
  • Experience evaluating and optimizing PPA trade-offs in memory designs.
  • Custom digital circuit design, simulation, layout design, and verification skills.
  • Familiarity with EDA tools used for custom digital and memory circuit design.

Preferred:

  • Design technology co-optimization (DTCO) experience.
  • Post-silicon validation and debugging experience.
  • Knowledge of the CMOS ASIC design flow.
  • PhD with 1–2 years of professional experience.

Education Requirements

Master's degree in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering, or a related discipline plus 4+ years of professional experience, OR a PhD in the same fields. The posting counts internships toward professional experience and indicates a PhD is an acceptable alternative to the master's-plus-experience route; preferred candidates may hold a PhD with 1–2 years' professional experience.


About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.

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Date Posted: 2026-06-23