Member of Technical Staff, Senior ASIC Verification

Job Title

Member of Technical Staff, Senior ASIC Verification

Role Summary

Lead ASIC verification efforts for Netpreme silicon, IP, and subsystems at an early-stage startup focused on memory acceleration for AI/datacenter applications. You will define verification methodology, drive verification from microarchitecture through tapeout, and coordinate across architecture, design, physical design, firmware, DFT, and post-silicon teams.

This role is onsite at the company offices in Santa Clara, CA or Boston, MA.

Experience Level

Senior — minimum 5+ years of ASIC/SoC verification experience.

Responsibilities

Primary responsibilities include planning and executing verification for IP and SoC, providing technical leadership, and coordinating cross-functional integration.

• Define and implement verification strategy and methodology from microarchitecture to tapeout.
• Verify silicon, IP blocks, and subsystems using simulation and verification flows.
• Conduct design and verification reviews; enforce best practices and quality standards.
• Collaborate with architecture, RTL design, physical design, firmware, DFT, and post-silicon teams to resolve issues and ensure system-level functionality.
• Interface with external IP vendors, foundries, and EDA/tool providers to manage dependencies and mitigate roadblocks.
• Drive PPA (power, performance, area) optimizations and integration of interconnect, I/O, and memory subsystems.
• Develop and maintain verification automation, scripts, and flow integration.

Requirements

Must-have technical skills, hands-on experience, and abilities required for the role.

• Minimum 5+ years of ASIC/SoC verification experience.
• Proven technical leadership in verification and simulation methodologies.
• Strong knowledge of the full ASIC/SoC development cycle from microarchitecture to tapeout in advanced process technologies.
• Outstanding expertise in verification methodologies and verification planning.
• Hands-on experience with industry protocol stacks (examples: Ethernet, UCIe, UALink).
• Experience optimizing designs for power, performance, and area; integrating major subsystems (interconnect, I/O, memory).
• Proficiency with front-end development tools and scripting for verification automation and flow integration.
• Excellent communication, leadership, and stakeholder management; ability to manage risks and escalations under tight schedules.
• Experience coordinating with external partners (IP vendors, foundries) and EDA tool providers.

Nice-to-have

• Verification and tapeout of advanced silicon devices.
• Post-silicon validation, debug, and manufacturing test experience.
• Knowledge of Design-For-Testability (DFT) and post-silicon debug/validation.
• Experience managing external design partners and foundry relationships.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field is required. PhD in a related field is preferred.

About the Company

Company: Netpreme

Headquarters: Santa Clara, CA, United States

Early-stage startup developing ASIC memory-acceleration solutions for AI and data-center workloads. Focused on designing high-performance silicon, IP and subsystems to improve efficiency and performance for large language models and other AI applications.