Member of Technical Staff, ASIC Design
NetpremeJob Title
Member of Technical Staff, ASIC Design
Role Summary
Senior ASIC designer on the Silicon Design team at an early-stage startup building memory-acceleration silicon for AI/datacenter applications. Responsible for IP/SoC microarchitecture, RTL development, implementation, and delivery, working onsite from Santa Clara, CA or Boston, MA.
Work involves cross-functional coordination across architecture, verification, physical design, firmware, DFT, and post-silicon validation.
Experience Level
Senior — typically 5+ years of ASIC/SOC digital design experience.
Responsibilities
Provide technical leadership and hands-on execution across the ASIC development cycle.
- RTL design of IPs, subsystems, and SoCs supporting the silicon roadmap.
- Define IP/SoC microarchitecture specifications and design methodologies; conduct design reviews.
- Optimize designs to meet aggressive performance, power, and area goals.
- Drive collaboration with architecture, verification, physical design, firmware, DFT, and post-silicon teams to ensure system-level functionality.
- Interface with external IP vendors, foundries, and EDA tool providers to address dependencies and roadblocks.
Requirements
Must-have technical skills and experience.
- Minimum 5+ years of ASIC/SOC digital design experience.
- Strong microarchitecture development and RTL coding skills (Verilog/SystemVerilog); synthesis and STA/timing closure experience.
- Experience with physical design and verification methodologies.
- Hands-on experience with industry protocol stacks (for example Ethernet, UCIe, UALink) or similar interfaces.
- Proven ability to optimize for PPA and integrate major subsystems (interconnect, I/O, memory).
- Proficiency with front-end development tools, scripting for automation, and flow integration.
- Experience coordinating across projects, managing risks, and meeting tight schedules.
- Design and tapeout experience in advanced process technologies is highly preferred.
Nice-to-have:
- Experience managing relationships with external design partners, IP vendors, and foundries.
- Knowledge of design-for-testability (DFT), post-silicon debug/validation, and manufacturing test.
Education Requirements
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field required; PhD in a related field preferred.
About the Company
Company: Netpreme
Headquarters: Santa Clara, CA, United States
Early-stage startup developing ASIC memory-acceleration solutions for AI and data-center workloads. Focused on designing high-performance silicon, IP and subsystems to improve efficiency and performance for large language models and other AI applications.
