Manager, Static Timing Analysis (STA)

Job Title

Manager, Static Timing Analysis (STA)

Role Summary

Lead and grow a team responsible for static timing analysis, timing closure, and timing signoff for advanced FPGA designs. Drive STA methodology, tools, and timing-driven optimizations while collaborating with RTL, synthesis, physical implementation, and architecture teams to meet performance, power, and schedule targets.

Experience Level

Senior — requires substantial domain experience (10+ years in STA) and leadership experience (3+ years managing engineering teams).

Responsibilities

The manager will own timing delivery, mentor engineers, and define STA strategy across multiple programs.

• Build, manage, and mentor a high-performing STA team; set technical direction and career development goals.
• Lead end-to-end STA for FPGA designs: develop constraints, perform timing analysis, and own timing signoff.
• Define and implement STA methodologies, flows, and best practices to improve timing convergence and signoff quality.
• Collaborate with RTL, synthesis, place & route, and architecture teams to identify and resolve timing issues.
• Drive performance, power, and area (PPA) improvements through timing-driven optimization.
• Use industry EDA timing tools to analyze violations, debug root causes, and automate flows (scripting where applicable).
• Manage timing milestones and ensure on-time delivery across multiple programs.

Requirements

Must-have technical and leadership qualifications; preferred skills listed separately.

• 10+ years of hands-on experience in Static Timing Analysis (STA) for ASIC or FPGA designs.
• 3+ years of experience managing or leading engineering teams.
• Deep knowledge of STA concepts including setup/hold analysis, clock domain crossing, and timing constraints.
• Strong experience with timing signoff tools (for example, PrimeTime or equivalent).
• Practical understanding of synthesis, place & route, and full-chip implementation flows.
• Familiarity with RTL (Verilog/SystemVerilog) and timing-closure methodologies.
• Skilled at root-cause analysis of timing violations and driving closure on complex designs.
• Preferred: FPGA architecture experience, advanced-node/high-speed design exposure, and scripting/automation (Tcl, Python).

Education Requirements

Bachelor's or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical field (as stated). Equivalent practical experience is not explicitly listed but may be considered.

Estimated salary range (Canada): CAD 144,600 – CAD 209,300 per year. The actual offer may vary based on location, experience, and other factors.

Note: AI may be used to screen or assess applicants. This posting is for an existing vacancy and Canadian work experience is not required. Applicants must be eligible for any required Canadian export authorizations.

About the Company

Company: Altera

Headquarters: Bengaluru, Karnataka, India

Altera provides leadership programmable solutions for applications ranging from cloud to edge, unveiling limitless AI possibilities. Their extensive product portfolio includes FPGAs, CPLDs, Intellectual Property, development tools, and System on Modules aimed at accelerating innovation in various fields.