Manager, FPGA Synthesis

Job Title

Manager, FPGA Synthesis

Role Summary

Lead a synthesis engineering team responsible for developing and optimizing logic synthesis within the FPGA compiler flow. The role focuses on delivering synthesis technology that improves performance, power, and area (PPA) for FPGA platforms and integrates with placement, routing, and timing flows.

Experience Level

Senior-level; requires approximately 10+ years in FPGA/ASIC design tools with emphasis on synthesis or logic optimization, and 5+ years managing engineering teams.

Responsibilities

Primary responsibilities include technical leadership, development, and cross-team integration within the FPGA toolchain:

• Build, manage, and mentor a synthesis engineering team; set technical direction and execution plans.
• Lead development and optimization of synthesis algorithms: logic optimization, mapping, and netlist generation.
• Own synthesis stages in the compiler and ensure integration with placement, routing, and static timing analysis (STA) flows.
• Drive QoR improvements across performance, power, and area through synthesis-driven optimizations.
• Guide RTL-to-gates transformation for Verilog/SystemVerilog/VHDL designs.
• Collaborate with architecture, placement, routing, and timing teams to align synthesis strategies with FPGA architecture.
• Oversee debugging of synthesis issues including timing bottlenecks, logic inefficiencies, and mapping challenges.
• Develop scalable synthesis methodologies, automation frameworks, and supporting tools.

Requirements

Must-have technical skills and experience:

• 10+ years experience in FPGA/ASIC design tools focused on synthesis or logic optimization.
• 5+ years experience managing or leading engineering teams.
• Deep knowledge of logic synthesis, optimization techniques, and mapping algorithms.
• Strong experience with RTL design (Verilog/SystemVerilog/VHDL).
• Familiarity with timing-driven synthesis and timing-closure methodologies.
• Proficiency in C/C++ and software engineering best practices.
• Experience integrating synthesis with downstream flows (placement, routing, STA).
• Proven ability to lead complex technical initiatives and deliver scalable, high-performance solutions.

Nice-to-have:

• Experience with Quartus or Vivado and understanding of FPGA architectures (LUTs, DSPs, BRAM, routing resources).
• Experience with advanced optimizations (retiming, resource sharing, logic restructuring).
• Familiarity with scripting for automation (Python, Tcl) and large-scale or distributed EDA development environments.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field. PhD candidates are encouraged to apply; relevant experience from doctoral studies may be counted toward the required years of experience.

About the Company

Company: Altera

Headquarters: Bengaluru, Karnataka, India

Altera provides leadership programmable solutions for applications ranging from cloud to edge, unveiling limitless AI possibilities. Their extensive product portfolio includes FPGAs, CPLDs, Intellectual Property, development tools, and System on Modules aimed at accelerating innovation in various fields.