Manager, Design Verification

Job Title

Manager, Design Verification

Role Summary

Lead a small team responsible for physical implementation and verification of complex SoC blocks. Own end-to-end block- and top-level physical design, delivery quality, and technical direction for implementation flows on advanced process nodes.

Role requires collaboration with RTL, STA, DFT, CAD, and packaging teams to resolve risks and converge on implementation-ready architectures. Travel ~10%.

Experience Level

Senior — typically 8–12+ years of experience in physical design or equivalent demonstrated expertise.

Responsibilities

Deliver technical ownership of block- and subsystem-level physical implementation and enable the team.

• Own floorplanning, power planning, placement, CTS, routing, ECO, and signoff activities for complex blocks and subsystems.
• Drive timing closure, congestion resolution, IR/EM, signal integrity, and physical verification (DRC/LVS/antenna) to meet PPA targets.
• Define and refine hierarchical PNR strategies, IO ring/PG structures, and SoC integration guidelines.
• Analyze and debug tool issues, timing failures, and physical anomalies; propose scalable solutions.
• Develop and maintain physical design methodologies, scripts, and automation for PDN, clocking, signoff, and exception handling.
• Provide technical direction, review team deliverables, and mentor junior engineers in PNR, STA, and debug practices.
• Coordinate with cross-functional teams and participate in design and signoff reviews to report status and mitigation plans.

Requirements

Must-have technical skills and leadership capabilities.

• 8–12+ years of hands-on physical design experience for complex digital SoCs.
• Proven experience with industry PNR and signoff tools (examples: Cadence Innovus, Synopsys ICC2, Tempus/PrimeTime, RedHawk, Voltus).
• Demonstrated success closing timing-, IR-, and congestion-critical blocks on advanced nodes (e.g., 22nm, 16nm, 7nm, 5nm, 4nm).
• Strong understanding of floorplanning, partitioning, power grid/PDN methodology, IR/EM mitigation, and advanced clock-tree/clock-mesh design.
• Experience with STA constraints (modes/corners, exceptions, derates) and physical verification/reliability checks.
• Problem-solving mindset with emphasis on scalable, automated solutions and clear technical communication.
• Experience mentoring engineers and providing technical leadership in a dynamic project environment.

Education Requirements

Not specified.

About the Company

Company: Analog Devices

Headquarters: Norwood, Massachusetts, USA

Analog Devices is a leading global semiconductor company that bridges the physical and digital worlds, enabling breakthroughs at the Intelligent Edge. With a focus on innovation, ADI develops solutions that drive advancements in digitized factories, mobility, and digital healthcare. The company employs around 24,000 people globally and reported revenues exceeding $9 billion in FY24, creating technologies that transform lives across various sectors.