Manager, ASIC Design Engineering (Starshield)

Job Title

Manager, ASIC Design Engineering (Starshield)

Role Summary

Lead a small engineering team that designs ASICs and FPGAs for Starshield satellite systems, owning architecture, RTL implementation, verification coordination, silicon bring-up, and operational support. Collaborate with modem/DSP, RF, verification, and physical-implementation teams to deliver timing-clean, high-performance chips for government space applications.

Base salary range: $190,000 - $245,000 per year; cleared candidates may receive an additional differential per the posting.

Experience Level

Senior — manager-level role. Posting requires 5+ years of RTL/ASIC/FPGA experience and 2+ years of direct-report management or equivalent leadership experience.

Responsibilities

Lead technical execution and people management across the ASIC/FPGA design lifecycle.

• Lead a small team responsible for digital ASIC and/or FPGA design for Starshield projects.
• Drive architectural trade-offs, derive subsystem specifications, and partition functions with modem/DSP and RF teams.
• Define micro-architecture, implement RTL in Verilog/SystemVerilog, integrate into top-level designs, and deliver fully verified, synthesis/timing-clean designs.
• Work closely with verification teams to ensure coverage and correctness.
• Provide timing constraints and support physical implementation teams (synthesis, timing closure, formality checks).
• Participate in silicon bring-up, validation, and development of automated test lab equipment.
• Recruit, develop, train, and retain engineering team members; coordinate with cross-functional leaders to meet product requirements.

Requirements

Must-have technical and leadership qualifications followed by preferred skills.

• 5+ years of experience in RTL implementation and/or FPGA/ASIC development.
• 2+ years of experience managing engineering staff or mentoring engineers with direct-report responsibility.
• Hands-on RTL design experience in Verilog/SystemVerilog and delivering synthesis- and timing-clean designs.
• Solid knowledge of synthesis, static timing analysis (STA), timing closure, and formality checking.
• Proven ability to collaborate with verification, DSP/modem, RFIC, and physical-design teams.

Nice-to-have:

• Experience with clock domain crossings, power optimization, and low-power design techniques.
• Experience developing complex ASICs, multicore CPU subsystems, embedded processors, and standard bus protocols (AXI, AHB).
• Familiarity with HDL simulators (VCS, Questa, IES), lint tools (Spyglass), and FPGA tools (Vivado, Quartus).
• Scripting skills (Python, TCL) and experience with EDA tool flows and automation.

Other requirements:

• Ability to work long hours and weekends as necessary to support critical milestones.
• Willingness to travel for off-site testing.
• Possession of or ability to obtain necessary U.S. government export authorizations may be required for certain programs; cleared candidates may be subject to pre-employment and random drug/alcohol testing.

Education Requirements

Bachelor's degree in electrical engineering, computer engineering, computer science, or another engineering discipline (as stated in the posting).

About the Company

Company: SpaceX

Headquarters: Hawthorne, California, United States

SpaceX is focused on developing space technologies to enable human exploration of Mars and beyond. The company is known for its advancements in rocketry and its Starlink satellite constellation, which delivers high-speed internet globally.