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Machine Learning SoC Architect

Meta Platforms
August 07, 2026
Full-time
On-site
Sunnyvale, California, United States
$212,000 - $294,000 USD yearly
SoC Architecture Jobs, Level - Senior

Job Title

Machine Learning SoC Architect

Role Summary

Join the Silicon Engineering organization to define architecture, performance modeling, and microarchitectural exploration for custom ASICs that serve Meta's data center and AI workloads. The role owns ASIC architecture specifications, performance methodology, and long-term silicon roadmap, working across silicon and software teams to meet throughput, latency, and efficiency targets at hyperscale.

Experience Level

Senior-level β€” 12+ years of relevant ASIC architecture and performance analysis experience.

Responsibilities

The role focuses on architecture definition, performance analysis, and validation of machine learning/data-center SoCs.

  • Analyze algorithms and workloads to derive architecture and performance requirements for ML ASICs.
  • Map data-center workloads to heterogeneous SoCs and calculate required compute throughput, memory bandwidth, and latency.
  • Drive architecture definition for subsystems (compute, memory, NoC, collectives, debug) and chiplet/multi-die SoC designs.
  • Select and run workloads and microbenchmarks on simulation and emulation platforms to validate architecture decisions.
  • Develop and apply pre-silicon performance models and microarchitectural analyses.
  • Collaborate with RTL, verification, firmware/software, post-silicon validation, and program management to deliver first-pass functional silicon.
  • Mentor architecture team members and present technical proposals to peers and leadership.

Requirements

Must-have technical experience and tools for the role; preferred items listed separately.

  • Must-have: 12+ years delivering high-performance ASICs into production with emphasis on architecture definition and performance analysis.
  • Deep knowledge of computer architecture concepts: microprocessor architecture, memory systems, on-chip interconnection networks, and hardware/software partitioning.
  • Experience in ASIC performance modeling, microarchitectural analysis, or pre-silicon simulation for custom SoC designs.
  • Proficiency in C++ and Python for building simulation models, automation, and performance analysis tools.
  • Experience analyzing data-center, AI accelerator, or HPC workloads on custom silicon.
  • Proven ability to define architecture and microarchitectural specifications and align cross-functionally with RTL and physical design teams.
  • Nice-to-have: post-silicon performance validation and model-to-hardware correlation experience.
  • Experience mapping hardware algorithms to efficient C/C++ implementations and familiarity with ML frameworks (example: PyTorch).
  • Domain knowledge in power/performance tradeoffs and building performance-modeling infrastructure for hyperscale ASICs (network, storage, or AI inference designs).

Education Requirements

Required: Bachelor's degree in Computer Science, Computer Engineering, or a relevant technical field, or equivalent practical experience. Preferred: Master's or PhD in Electrical Engineering, Computer Engineering, or a related field.


About the Company

Company: Meta Platforms

Headquarters: Menlo Park, California, United States

American technology company that develops social networking products (Facebook, Instagram, WhatsApp) and invests in virtual/augmented reality hardware and software through Reality Labs, focusing on connectivity, advertising, and immersive computing experiences.

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Date Posted: 2026-08-07