Low Power Design/Methodology Engineer
Engineer role within Qualcomm's ASICs engineering group focused on digital low-power IP for SoC integration. The position covers RTL implementation, power-aware design methodology, and collaboration with circuit, verification, and physical design teams to deliver low-power controllers and power models.
Position is based in San Diego, CA and supports wireless and automotive SoC products, including functional-safety-related features.
Mid-level β typically 2β4 years of relevant ASIC/low-power design experience; the posting specifies multiple years of experience in low-power digital ASIC design.
Key responsibilities include implementation and integration of low-power IP and development of low-power design methods.
Concise list of required technical skills and experience. Degrees are summarized separately under Education Requirements.
Bachelor's degree in Science, Engineering, or a related field with 2+ years of relevant experience; OR Master's degree in a related field with 1+ year of relevant experience; OR PhD in a related field. (Degrees are those explicitly listed in the source posting.)
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
