Low-Power Design Engineer
VoltaiJob Title
Low-Power Design Engineer
Role Summary
The Low-Power Design Engineer will own power intent from architecture through signoff for SoCs and IP, designing and verifying low-power architectures on production silicon. The role partners with RTL, physical design, and signoff teams and contributes to automation and evaluation of AI-generated power intent.
The team works on hardware and semiconductor systems where AI is applied to power-aware design and verification.
Experience Level
Mid-level - 5+ years of relevant low-power design or verification experience (production tapeouts preferred).
Responsibilities
Primary responsibilities include defining and validating power intent, running power-aware checks, and collaborating across implementation and signoff teams.
- Define power architecture and author UPF power intent for SoCs and IP.
- Implement and verify power gating, clock gating, multi-voltage domains, and retention strategies.
- Run power-aware simulation, static low-power checks, and CDC/RDC analysis.
- Collaborate with RTL, physical design, and signoff teams on power estimation and closure.
- Build automation for power analysis, reporting, and signoff-ready flows.
- Evaluate AI-generated power intent and help define correctness criteria.
Requirements
Must-have technical skills and experience:
- 5+ years of low-power design or verification experience on production tapeouts.
- Expert knowledge of UPF and power-aware verification methodologies.
- Hands-on experience with power analysis tools such as VC LP, Conformal Low Power, or PowerArtist.
- Experience with CDC/RDC analysis tools (e.g., SpyGlass, Questa CDC, or similar).
- Python or Tcl scripting for automation and data processing.
Nice-to-have:
- Experience with mobile, edge, or data-center power management.
- Formal verification of power intent.
- Interest or experience with AI-assisted design tools.
Education Requirements
Not specified.
About the Company
Company: Voltai
Headquarters: Palo Alto, CA, United States
Voltai develops AI-driven world models and agents to design, evaluate, and optimize physical systems-focusing on hardware, electronics, and semiconductors to enable AI-led hardware co-design, performance modeling, and cross-domain optimization.
