Logic Designer / Integrator / Tester

Job Title

Logic Designer / Integrator / Tester

Role Summary

Design, integrate, and validate digital logic for ASIC/FPGA projects. Work with SoC/IP teams to integrate blocks, create verification environments, and support bring-up and silicon validation.

Collaborate with architects, physical design, verification, and test engineering to meet functional, timing, and quality targets.

Experience Level

Mid-level. Years of experience not specified.

Responsibilities

Core responsibilities include design, integration, verification, and debug of digital logic and IP blocks.

• Develop and review RTL (e.g., Verilog/SystemVerilog) for new and existing IP blocks.
• Integrate IP into top-level designs and SoC environments; resolve integration issues.
• Create and run verification/testbench environments and directed/random tests.
• Perform bring-up and debug support for FPGA prototyping and silicon validation.
• Work with EDA tools for synthesis, linting, and simulation; participate in timing closure reviews.
• Document designs, test results, and integration procedures; hand off to downstream teams.

Requirements

Must-have skills and experience necessary to perform the role; plus common nice-to-have items.

• Practical experience with RTL design and coding in Verilog or SystemVerilog.
• Experience with IP integration, SoC/top-level integration, and debug workflows.
• Familiarity with verification methodologies and simulation tools; ability to create testbenches.
• Scripting skills for automation and test development (e.g., Python, Tcl, shell).
• Ability to work with FPGA prototyping and perform root-cause analysis of functional issues.

Nice-to-have:

• Experience with timing closure, synthesis flows, and common EDA tools.
• Familiarity with low-power design techniques, formal verification, or hardware bring-up.
• Experience with Linux environments and debug tools.

Education Requirements

Not specified.