LLM Fine-Tuning Engineer (Verilog/RTL)

Job Title

LLM Fine-Tuning Engineer (Verilog/RTL)

Role Summary

Machine Learning Engineer responsible for fine-tuning and deploying LLM-based features that operate on Verilog/RTL and similar hardware-description artifacts. The role owns the technical roadmap, designs ML pipelines, and delivers production model integrations within an engineering team.

Experience Level

Mid-senior level. The posting indicates a mid-senior role but does not specify exact years of experience.

Responsibilities

Primary responsibilities include designing, building, and operating ML systems for Verilog/RTL use cases:

• Design and implement LLM fine-tuning workflows tailored to Verilog/RTL datasets.
• Own the technical roadmap and lead ML/AI projects end-to-end.
• Design and build ML training and serving pipelines on AWS (training, inference, monitoring).
• Deploy LLM-powered features to production and manage model lifecycle and monitoring.
• Collaborate with hardware, firmware, and software teams to integrate models into products.
• Establish data preprocessing, labeling, evaluation metrics, and CI for models.
• Optimize training and serving performance, costs, and observability.

Requirements

Required and preferred skills and experience:

• Must-have: Proven experience fine-tuning and deploying LLMs in production.
• Demonstrated ML/AI background with experience leading projects and delivering features.
• Experience building ML pipelines and model serving on AWS.
• Proficiency in Python and ML frameworks such as PyTorch or TensorFlow; familiarity with Hugging Face tooling.
• Experience with code models or working with code corpora; familiarity with Verilog/RTL or other hardware description languages.
• Strong software engineering practices, version control, and CI/CD for ML systems.
• Nice to have: Experience with EDA tools, RLHF, retrieval-augmented generation, and large-scale training workflows.

Education Requirements

Not specified.

About the Company

Company: Beacon Industries

Technology/engineering company focused on analog and mixed-signal integrated circuit design and custom IC layout (SerDes, SRAM, high-speed interfaces), using Synopsys/Cadence EDA tools for design, simulation, verification, and silicon validation.