LLM Fine-Tuning Engineer (Verilog/RTL)

Job Title

LLM Fine-Tuning Engineer (Verilog/RTL)

Role Summary

Lead development and deployment of LLM-based features focused on Verilog/RTL workflows. Define the technical roadmap and build production ML pipelines and services.

Onsite role in San Jose, CA. Responsible for end-to-end model fine-tuning, evaluation, integration with developer tooling, and driving cross-functional delivery.

Experience Level

Mid-senior level (Mid-Career). The posting requests significant ML/AI and LLM fine-tuning experience; specific years of experience were not provided.

Responsibilities

Key responsibilities:

• Own the technical roadmap for LLM-powered Verilog/RTL features.
• Design and implement ML pipelines on AWS for training, fine-tuning, and inference.
• Fine-tune, evaluate, and validate large language models on Verilog/RTL datasets.
• Deploy, monitor, and maintain production LLM services and features.
• Collaborate with RTL engineers and product teams to integrate models into developer workflows and tools.
• Lead projects, make technical decisions, and mentor other engineers.

Requirements

Must-have and preferred qualifications:

• Must-have: Proven experience in ML/AI with LLM fine-tuning and production deployments.
• Must-have: Experience applying ML to code or hardware description languages (Verilog/RTL) or similar domains.
• Must-have: Experience designing ML pipelines and deploying models on AWS.
• Must-have: Track record of delivering LLM-powered features to production and leading technical projects.
• Nice-to-have: Experience with PyTorch, TensorFlow, Hugging Face Transformers, and prompt engineering.
• Nice-to-have: Familiarity with MLOps tooling, Docker/Kubernetes, dataset curation, and evaluation for code/RTL.

Education Requirements

Not specified.

About the Company

Company: CaritaTech

Engineering staffing and consulting firm providing placement and contract services for hardware, semiconductor, and embedded systems professionals, including roles in SoC/ASIC physical design and verification.