Linux Kernel Architect

Job Title

Linux Kernel Architect

Role Summary

Design, improve, and debug the Linux kernel and related system firmware for RISC-V platforms with emphasis on high core-count server systems. Work upstream with the Linux and OpenSBI communities, collaborate with system software, validation teams, and hardware architects to diagnose and resolve software/hardware interactions in emulation and silicon.

Experience Level

Senior — experienced kernel architect (typical expectation: 7+ years of relevant experience).

Responsibilities

Primary technical responsibilities for this role include implementation, debugging, and upstream collaboration.

• Maintain and improve the RISC-V Linux kernel, focusing on scalability and concurrency for high core-count systems.
• Identify, reproduce, and debug complex software and hardware interactions in CPUs and SoCs.
• Develop, test, and debug Linux on FPGA and emulation platforms.
• Prepare, post, and review patches on upstream Linux and OpenSBI mailing lists; follow upstream review processes.
• Collaborate with system software, validation teams, and hardware architects to isolate issues and define fixes.
• Work with hardware and firmware teams to validate and improve core and system designs for Linux support.
• Support virtualization and hypervisor integration efforts on RISC-V platforms.

Requirements

Must-have skills and experience are listed first; desirable skills follow.

• Must-have: Experience working on concurrency-sensitive code in the upstream Linux kernel, with a track record of writing and reviewing patches on public mailing lists.
• Must-have: Proven experience debugging challenging software and hardware bugs in CPUs and SoCs.
• Must-have: Experience collaborating with CPU architects and RTL engineers.
• Must-have: Experience developing and debugging Linux on FPGA and emulation platforms.
• Must-have: Experience with hypervisors and virtualization technologies.
• Must-have: Familiarity with the RISC-V architecture.
• Nice-to-have: Familiarity with silicon design issues and microarchitectural side-channel mitigations.
• Nice-to-have: Experience using hardware debuggers and low-level debug tools.
• Nice-to-have: Familiarity with Devicetree, ACPI, UEFI, and Rust.

Education Requirements

Not specified.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.