Lead Verification Engineer

Job Title

Lead Verification Engineer

Role Summary

Senior verification specialist responsible for validating AI-generated verification artifacts and ensuring interoperability with standard semiconductor verification workflows and EDA tools. Acts as a subject-matter expert for verification methodology, debugging customer issues, and developing benchmark datasets for AI model evaluation.

Work closely with customers, application and product teams, and AI/LLM engineers to qualify AI outputs, reduce technical errors, and integrate AI-assisted automation into simulation, coverage, and formal flows.

Experience Level

Senior - typically 6–10 years of semiconductor verification experience (as specified in the posting).

Responsibilities

The role validates verification workflows, supports customers, builds benchmark datasets, and enables AI model integration into EDA flows.

• Validate AI-generated outputs across RTL verification workflows, including UVM testbenches, SVA assertions, coverage strategies, and simulation/formal flows.
• Investigate, reproduce, and debug customer-reported verification issues (UVM environments, testbenches, assertion failures, regressions) and document root causes.
• Develop and maintain golden reference test cases and benchmark verification datasets; define correctness criteria and build validation suites for model qualification and regression testing.
• Collaborate with AI/LLM engineers to review model responses, provide feedback, and translate verification workflows into structured AI evaluation scenarios to reduce hallucinations and improve technical correctness.
• Validate interoperability between AI systems and EDA tools; support automation across simulation, regression management, coverage analysis, and formal verification.
• Identify opportunities to improve verification productivity through AI-assisted automation and workflow integration.

Requirements

Key must-have technical skills and experience for immediate effectiveness in this role.

• Must-have: 6–10 years of semiconductor verification experience with proven experience developing and debugging complex UVM-based verification environments.
• Must-have: Hands-on RTL verification experience at IP, subsystem, or SoC level; strong knowledge of SystemVerilog, UVM, functional and code coverage, assertion-based verification (SVA), and constrained-random methodologies.
• Must-have: Deep debugging skills for simulation failures, assertion violations, coverage gaps, verification regressions, and multi-component testbenches.
• Must-have: Scripting and automation skills: Python, shell scripting, TCL; experience building workflow and test framework automation.
• Must-have: Practical experience with one or more EDA tools such as Cadence Xcelium, Synopsys VCS, Siemens QuestaSim, Cadence JasperGold, Synopsys VC Formal, or verification/regression platforms.
• Nice-to-have: Experience supporting customers or field engineering organizations and exposure to EDA product development or application engineering.
• Nice-to-have: Familiarity with AI, LLMs, AI-assisted EDA workflows, agentic AI systems, and evaluation methodologies.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline (as stated in the posting).

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.