Lead Systems Signal Integrity/Power Integrity Engineer

Job Title

Lead Systems Signal Integrity/Power Integrity Engineer

Role Summary

Lead technical SI/PI engineering across system-level AI compute platforms, focusing on chip-to-chip and chip-to-board interfaces, power delivery networks, flex/rigid-flex interconnects, connectors, and advanced packaging.

The role combines hands-on analysis, simulation-to-hardware correlation, and cross-team technical leadership to resolve high-impact signal and power integrity issues for next-generation AI systems.

Experience Level

Senior — requires significant senior-level experience. The posting specifies 15+ years of system-level SI/PI engineering experience.

Responsibilities

Primary responsibilities include advanced analysis, troubleshooting, and design guidance across boards, flex circuits, packages, and connectors.

• Solve complex SI/PI problems for high-speed AI compute platforms (chip-to-chip, chip-to-board).
• Perform pre-layout and post-layout SI/PI analysis for PCBs, rigid-flex, and flex designs.
• Lead root-cause analysis for margin shortfalls, impedance discontinuities, coupling, resonances, and simulation-to-hardware mismatches.
• Troubleshoot and optimize power delivery networks using DC/AC simulations and lab correlation.
• Define and refine stack-ups, materials, and impedance targets for PCB and flex assemblies.
• Review schematics and layouts to identify SI/PI risks and recommend design changes.
• Coordinate with silicon and package teams on bump/ball assignments and package-to-PCB transitions.
• Serve as technical escalation point for complex SI/PI issues across programs.

Requirements

Must-have technical skills and domain experience. Preferred items noted.

• Deep expertise in high-speed serial and parallel interface analysis and debug.
• Hands-on experience with PCB, rigid-flex, and flex circuit stack-up design and analysis.
• Experience analyzing flex connectors, high-density interconnects, interposers, and advanced packaging technologies.
• Proficiency with 2D and 3D electromagnetic simulation tools and transmission-line/microwave fundamentals.
• System-level PDN analysis, simulation, and lab correlation skills.
• Proven ability to correlate simulation results with hardware behavior and drive design fixes.
• Practical lab debugging experience and use of relevant measurement equipment.
• Domain experience with server hardware, AI accelerators, datacenter platforms, or similar high-performance compute systems.
• Nice-to-have: prior work on large-scale AI or HPC systems and familiarity with interposer/advanced-package tradeoffs.

Education Requirements

Master's degree in Electrical Engineering (required, per posting). No alternative "or equivalent experience" language was provided in the source.

About the Company

Company: Cerebras

Headquarters: Sunnyvale, CA, USA

Developer of wafer-scale AI accelerators, Cerebras designs the Wafer Scale Engine (WSE)—one of the world’s largest AI chips—to deliver high-speed training and inference solutions for model labs, enterprises, and AI-native startups.