Lead RTL Design Engineer

Job Title

Lead RTL Design Engineer

Role Summary

Lead front-end RTL engineer responsible for designing, integrating, and delivering high-performance, power-efficient ASIC RTL for next-generation wafer-scale AI processors. The role partners with physical design, verification, software and systems teams and manages external ASIC vendors through product development to production.

Experience Level

Senior; 8–15 years of relevant RTL/ASIC design experience as stated in the posting.

Responsibilities

Key responsibilities include:

• Define functional specifications and micro-architecture; develop and maintain RTL.
• Perform synthesis and front-end integration to meet performance, power, and area targets.
• Manage and coordinate with external ASIC vendors throughout the product development cycle.
• Collaborate with physical design (PD) to achieve PPA and design closure.
• Work with verification and DFT teams to maximize functional and test coverage.
• Partner with software and system teams to optimize performance and feature set.
• Debug silicon-level functional, timing, and power issues during bring-up.

Requirements

Must-have skills and experience:

• 8–15 years delivering complex, high-performance RTL designs.
• Deep expertise in RTL design, front-end chip integration, and third-party IP integration.
• Proven track record of multiple silicon successes and experience debugging silicon bring-up issues.
• Experience collaborating with and managing external vendors.
• Experience with high-speed I/O and SerDes technologies; knowledge of PCIe and CPU interfaces.
• Networking stack experience (TCP/IP, RDMA, Ethernet) and experience in networking, HPC, or machine learning domains.
• Working knowledge of scripting tools such as Python and TCL.
• Ability to work in a hybrid work environment.

Nice-to-have:

• Experience with FPGA toolchains including place-and-route, floorplanning, and timing analysis.

Education Requirements

Master's degree in Computer Science, Electrical Engineering, or a related field, or equivalent practical experience.

About the Company

Company: Cerebras

Headquarters: Sunnyvale, CA, USA

Developer of wafer-scale AI accelerators, Cerebras designs the Wafer Scale Engine (WSE)—one of the world’s largest AI chips—to deliver high-speed training and inference solutions for model labs, enterprises, and AI-native startups.