Lead RTL Design Engineer

Job Title

Lead RTL Design Engineer

Role Summary

Lead front-end RTL engineer responsible for designing and integrating high-performance, power-efficient RTL for Cerebras Wafer Scale Engine (WSE) products. The role includes RTL development, microarchitecture work, synthesis, and close collaboration with verification, physical design, software, and system teams.

The position requires managing external ASIC vendor relationships and resolving silicon bring-up issues to move designs from specification to production.

Experience Level

Senior level — typically 8–15 years of related experience delivering complex, high-performance RTL designs.

Responsibilities

The role leads front-end chip development and cross-functional integration to meet performance, power, and area goals.

• Drive RTL architecture, micro-architecture, specification, development, and synthesis for chip blocks.
• Manage and coordinate activities with external ASIC vendor through the product development cycle.
• Integrate third-party IP and lead front-end chip integration tasks.
• Work with physical design (PD) to achieve PPA and design closure.
• Collaborate with design verification and DFT teams to maximize functional and test coverage.
• Work with software and systems teams to identify performance and feature trade-offs.
• Debug silicon-level functional, timing, and power issues during bring-up.

Requirements

Key technical and professional requirements. Items labeled "Must-have" are required; "Nice-to-have" are preferred.

Must-have:

• 8–15 years delivering complex, high-performance RTL designs and integrations.
• Deep expertise in RTL design, synthesis, and front-end integration.
• Experience integrating third-party IP and collaborating with external vendors.
• Proven track record of multiple silicon tapeouts/successful silicon projects.
• Experience or domain knowledge in networking, high-performance computing, or machine learning workloads.
• Experience with high-speed IO design and integration; familiarity with SerDes, PCIe, and CPU interfaces.
• Networking protocol experience (TCP/IP, RDMA, Ethernet).
• Scripting proficiency (Python, TCL) for design and automation tasks.
• Ability to work in a hybrid work environment and coordinate across distributed teams.

Nice-to-have / Assets:

• Experience with FPGA toolchains and FPGA-based bring-up.
• Familiarity with place-and-route, floorplanning, and timing analysis flows.

Education Requirements

Master's degree in Computer Science, Electrical Engineering, or equivalent; equivalent practical experience accepted.

About the Company

Company: Cerebras

Headquarters: Sunnyvale, CA, USA

Developer of wafer-scale AI accelerators, Cerebras designs the Wafer Scale Engine (WSE)—one of the world’s largest AI chips—to deliver high-speed training and inference solutions for model labs, enterprises, and AI-native startups.