Lead Product Engineer

Job Title

Lead Product Engineer

Role Summary

Drive timing signoff and engineering-change-order (ECO) flows for advanced SoC tapeouts, working with R&D, physical design, CAD, and foundry partners. Focus on static timing analysis (STA), timing closure, signoff accuracy, and physical-aware ECO implementation using industry signoff tools.

Work includes advanced-node enablement (5nm, 3nm, 2nm), automation of timing workflows, and participation in AI-enabled workflow improvements.

Experience Level

Senior - typically 4–6 years of experience in STA and timing closure.

Responsibilities

Primary responsibilities include timing signoff, closure, correlation, and automation for large-block and full-chip designs.

• Perform static timing analysis across MMMC scenarios (block and full-chip).
• Debug setup/hold violations, signal-integrity, and variation-related timing issues.
• Drive timing closure using PBA/GBA and advanced derating techniques.
• Implement physical-aware timing ECOs and optimize power/performance/area (PPA).
• Perform STA vs SPICE correlation to improve signoff accuracy.
• Support foundry enablement and technology node bring-up (5nm, 3nm, 2nm).
• Collaborate with P&R, CAD, verification, and foundry teams to resolve cross-domain issues.
• Develop and maintain automation for timing workflows using Tcl and Python.
• Contribute to AI/automation initiatives (basic LLM/agent understanding and CLI-based automation exposure preferred).

Requirements

Must-have technical skills and experience to perform the role.

• Must-have: 4–6 years of hands-on experience in STA and timing closure for large SoCs.
• Must-have: Strong hands-on experience with PrimeTime and Tempus.
• Must-have: Solid understanding of MMMC methodologies, OCV/AOCV/SOCV, and LVF.
• Must-have: Proficiency in Python and/or Tcl scripting for automation.
• Must-have: Strong debugging skills in large SoC environments and experience collaborating with P&R and CAD teams.
• Must-have: Experience with foundry interactions and technology node enablement.
• Nice-to-have: SPICE simulation and STA vs SPICE correlation experience.
• Nice-to-have: Exposure to AI/LLM concepts and interest in intelligent workflow automation.

Education Requirements

B.Tech / M.Tech / PhD in Electrical / Electronics Engineering (degrees listed in the original posting). These are the stated educational expectations for the role.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.