Lead Principal Engineer, Layout Design

Job Title

Lead Principal Engineer, Layout Design

Role Summary

Lead the physical implementation and signoff of DRAM and mixed-signal memory products, translating schematics and specifications into manufacturable layouts. Collaborate with circuit designers, verification, CAD/methodology, process integration, and test teams to meet power, performance, area, reliability, and time-to-market targets.

Experience Level

Senior-level — requires significant experience in semiconductor layout; the posting specifies 10+ years of industry experience.

Responsibilities

The role leads layout implementation across blocks and top-level integration and drives tapeout readiness.

• Lead layout build and physical realization of new memory products (analog, digital, and memory-array circuitry).
• Develop hierarchical block and top-level floorplans to optimize placement, routing, signal/power integrity, and manufacturability.
• Implement custom layout solutions to meet PPA and reliability targets; optimize for die area, matching, coupling/noise, and timing.
• Run and debug physical verification flows, perform parasitic extraction, and close PEX/signoff issues.
• Resolve layout issues related to signal integrity, crosstalk, antenna effects, and power integrity.
• Drive and document standard physical-build practices and tool flows; create layout collateral for cross-team integration.
• Plan resources, set priorities, and coordinate ECO execution to meet tapeout schedules; report status to technical leadership.
• Automate layout tasks and improve tool flows through scripting.

Requirements

Must-have technical skills and experience for immediate success in the role.

• 10+ years of semiconductor industry experience, including hands-on custom IC layout and physical verification work.
• Strong understanding of CMOS devices and layout-dependent effects, plus reliability checks and layout constraints.
• Experience leading technical execution and delivering tapeouts; able to coordinate with multi-discipline teams.
• Proficiency with industry-standard EDA layout and physical-verification tools and scripting/automation to improve efficiency.
• Ability to perform parasitic extraction analysis and assess impact on timing, power, and functionality.

Nice-to-have:

• Deep knowledge of advanced-node layout considerations and memory/storage technology trends.
• Excellent problem-solving, debugging, and communication skills.
• Experience mentoring or setting layout methodology for future generations of products.

Education Requirements

Minimum: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience. Preferred: Master's or PhD in Electrical/Computer Engineering or related field, or equivalent experience in lieu of an advanced degree. (No specific certifications were listed.)

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.