Lead PPA Engineer
FractileJob Title
Lead PPA Engineer
Role Summary
Lead the performance, power and area (PPA) closure for datapath blocks in high-performance AI/ML accelerator silicon. Translate PPA targets into microarchitectural and RTL changes, drive timing closure, and validate impact across synthesis and implementation flows.
Work closely with physical design, verification, synthesis and modelling teams to deliver measurable PPA improvements. This role may require export-control eligibility checks.
Experience Level
Senior / Lead level. No specific years of experience stated.
Responsibilities
Primary responsibilities include delivering measurable PPA improvements and driving datapath closure end-to-end.
- Identify datapath bottlenecks and define microarchitectural or RTL changes to meet PPA targets.
- Implement timing-aware datapath RTL and iterate against synthesis/STA feedback to close critical paths.
- Perform PPA trade-off analysis and translate targets into RTL and microarchitecture decisions.
- Collaborate with physical design, verification, synthesis and IP teams during PPA closure.
- Validate impact of changes against targets using synthesis, modelling and silicon data.
- Apply low-power design techniques and iterate to balance performance, power and area.
Requirements
Must-have technical skills and experience:
- Strong datapath microarchitecture background: pipelining, retiming, parallelism vs area trade-offs.
- Track record of driving datapath PPA closure end-to-end with measurable results on production datapath or compute silicon.
- Knowledge of fixed-point, floating-point and/or quantized arithmetic design.
- Deep understanding of PPA trade-offs and the ability to convert targets into RTL/microarchitectural decisions.
- Experience writing timing-aware datapath RTL and iterating with synthesis/STA feedback.
- Familiarity with synthesis tools (e.g. Synopsys Design Compiler/Fusion Compiler, Cadence Genus) and datapath IP/generator libraries (e.g. DesignWare).
- Experience with formal verification or equivalence checking.
- Physical design awareness sufficient to collaborate effectively with PD engineers.
Nice-to-have:
- Experience with AI/ML accelerator datapaths (systolic arrays, MAC/tensor engines) or other high-performance compute architectures.
- Experience with static timing analysis tools (e.g. PrimeTime, Tempus).
Education Requirements
Not specified.
About the Company
Company: Fractile
Headquarters: London, UK
Fractile is on a mission to revolutionize AI by developing silicon, systems, and software that enable the fastest execution of advanced models at lower costs. Established in 2022, the company has rapidly expanded, fostering a collaborative culture in its London and Bristol offices. With a focus on innovation in ML/AI IC product development, Fractile combines hardware and software to deliver high-impact solutions for data center applications.
