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Lead Physical Design Engineer

NXP Semiconductors
October 13, 2026
Full-time
On-site
Pune, Maharashtra, India
Physical Design Jobs, Level - Senior

Job Title

Lead Physical Design Engineer

Role Summary

Lead and execute RTL synthesis and Static Timing Analysis (STA) for complex SoC designs. Own timing closure, sign-off activities, and development of STA methodologies and flows across block, subsystem, and SoC levels.

Work closely with design, DFT, physical design, and verification teams; provide technical leadership and mentor junior engineers.

Experience Level

Senior level - approximately 10 years of relevant experience.

Responsibilities

Primary accountabilities for the role include:

  • Lead RTL synthesis and perform comprehensive static timing analysis at block, sub-system, and SoC levels.
  • Create, integrate, and maintain timing constraints (SDC) across design hierarchies.
  • Identify, debug, and resolve timing violations including setup, hold, and advanced checks (OCV, AOCV, EMIR, X-talk).
  • Develop, implement, and maintain STA methodologies, flows, and automation scripts to improve productivity and turnaround.
  • Perform timing sign-off and produce comprehensive timing reports for reviews.
  • Collaborate with design, DFT, physical design, and verification teams to meet project schedules and timing closure.
  • Mentor and provide technical guidance to junior engineers.
  • Keep current with industry best practices and emerging STA/physical-design techniques.

Requirements

Core qualifications and skills required and helpful for successful performance:

  • Must-have: ~10 years of experience in RTL synthesis and static timing analysis for complex SoC designs.
  • Must-have: Proven experience developing and maintaining timing constraints (SDC) and performing timing sign-off.
  • Must-have: Strong debugging skills for setup/hold and advanced timing issues (OCV/AOCV/EMIR/X-talk).
  • Must-have: Experience creating STA methodologies, flows, and automation to accelerate closure.
  • Must-have: Demonstrated ability to collaborate across design, DFT, physical design, and verification teams and to produce timing reports.
  • Must-have: Experience mentoring or leading junior engineers.
  • Nice-to-have: Familiarity with STA automation and scripting, and experience improving STA turnaround and flow integration.

Education Requirements

Not specified.


About the Company

Company: NXP Semiconductors

Headquarters: Nijmegen, Netherlands

NXP Semiconductors N.V. is a global semiconductor company that provides High Performance Mixed Signal and Standard Product solutions. With over 45,000 employees and operations in more than 35 countries, NXP is a leader in secure connectivity solutions for embedded applications, catering to automotive, industrial IoT, mobile, and communication infrastructure markets. The company is committed to innovation and sustainability, advancing a smarter, safer, and more sustainable world through technology.

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Date Posted: 2026-10-09