Lead Physical Design Engineer

Job Title

Lead Physical Design Engineer

Role Summary

Lead implementation of complex ASIC/SoC physical designs from synthesis through sign-off, optimising performance, power, and area (PPA). Work closely with RTL, verification, DFT, and foundry/process teams and may take ownership of full-chip execution.

Role may require export-control eligibility checks due to regulated technologies.

Experience Level

Senior / Principal level. The posting specifies ~10+ years of physical design experience for advanced technology nodes.

Responsibilities

Core hands-on physical-design duties and cross-team coordination.

• Drive floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off; potential full-chip execution responsibility.
• Perform synthesis, STA and timing closure activities to meet PPA targets.
• Plan and analyse power, addressing IR drop, EM, and multi-power-domain designs.
• Ensure DRC/LVS and other physical verification compliance for manufacturability.
• Integrate DFT structures with physical implementation and collaborate with DFT engineers.
• Develop and maintain flows in EDA tools (place & route, STA, sign-off, physical verification).
• Interface with foundries and process engineers to optimise yield and process compatibility.
• Work with RTL and architecture teams on physical-aware RTL constraints and feasibility.
• Adopt and apply advanced AI tools to improve productivity and design quality where appropriate.

Requirements

Must-have skills and practical experience; a short list of desirable extras.

• Must-have: Extensive hands-on physical design experience at advanced nodes (place & route, CTS, routing, sign-off, STA).
• Must-have: Strong proficiency with EDA tools for P&R, STA and sign-off (experience with tools such as Cadence Innovus, Synopsys Fusion Compiler, Calibre is expected).
• Must-have: Deep understanding of CMOS technology, timing closure, signal integrity, IR-drop analysis and low-power techniques.
• Must-have: Practical experience with power planning, EM/IR mitigation, and multi-power-domain architectures.
• Must-have: Scripting and automation skills (TCL, Python, Perl or similar) to build and maintain flows.
• Must-have: Strong problem-solving, communication, and teamwork in cross-functional IC design teams.
• Nice-to-have: Experience with HPC, AI accelerators, networking chips, or use of AI/ML tools in engineering workflows.

Education Requirements

Bachelor’s, Master’s or PhD in Electrical Engineering, Computer Engineering, or a related technical field.

About the Company

Company: Fractile

Headquarters: London, UK

Fractile is on a mission to revolutionize AI by developing silicon, systems, and software that enable the fastest execution of advanced models at lower costs. Established in 2022, the company has rapidly expanded, fostering a collaborative culture in its London and Bristol offices. With a focus on innovation in ML/AI IC product development, Fractile combines hardware and software to deliver high-impact solutions for data center applications.