Skip to main content
Rambus logo

Lead Member of Technical Staff – Logic Design

Rambus
November 5, 2026
Full-time
Remote friendly (Hillsboro, Oregon, United States)
Worldwide
RTL Design Jobs, Level - Senior

Job Title

Lead Member of Technical Staff – Logic Design

Role Summary

Individual contributor on the Silicon IP (SIP) team responsible for micro-architecture and RTL design of high-performance memory controller blocks for data center and AI applications. The role partners with verification, physical design, and customer-facing teams to deliver production-ready silicon IP.

Experience Level

Senior-level engineering role. Typical experience: 8+ years of logic design (ASIC/FPGA); hiring flexibility noted for candidates with advanced degrees.

Responsibilities

Design and deliver RTL for critical controller blocks and drive architecture decisions based on quantitative trade-offs.

  • Define micro-architecture and implement RTL for schedulers, command pipelines, coherency/ordering logic, and system interfaces.
  • Analyze performance, power, and area (PPA) trade-offs and recommend design choices supported by data.
  • Collaborate with verification to shape test plans, improve coverage, and debug regression failures; provide RTL fixes as needed.
  • Work with physical design to resolve timing, power, and congestion issues.
  • Provide technical support to pre-sales (FAE) and post-sales (AE) customer engagements.

Requirements

Key technical and professional requirements; degrees and academic expectations are summarized under Education Requirements below.

  • 8+ years of logic design experience (ASIC/FPGA).
  • Strong SystemVerilog/Verilog RTL design expertise.
  • Experience with Questa, Incisive, or VCS simulators.
  • Scripting proficiency in Python, Perl, or TCL.
  • Experience analyzing PPA and driving design trade-offs.
  • Proven ability to collaborate with verification and physical design teams; debug regressions and implement RTL fixes.
  • Solid communication and project management skills; ability to learn quickly and work independently.
  • Nice-to-have: ASIC synthesis and timing-constraint experience, CDC/RDC, UVM verification, HBM/LPDDR memory expertise, AMBA AXI or CHI protocol experience.

Education Requirements

Bachelor of Science in Electrical Engineering (BSEE) or Master of Science in Electrical Engineering (MSEE) are cited in the posting: BSEE with ~8+ years relevant experience or MSEE with ~6+ years relevant experience. Fields referenced: Electrical Engineering or closely related technical disciplines.


About the Company

Company: Rambus

Headquarters: Sunnyvale, California, USA

Rambus is a global leader in advanced semiconductor and technology solutions, specializing in enhancing data access and improving performance in computing, networking, and storage applications. The company is known for its innovative IP and solutions in memory, security, and interface technologies. With a strong focus on research and development, Rambus continues to push the boundaries of technology to meet the growing demands of the digital age.

Rambus logo

Date Posted: 2026-11-04