Lead Member of Technical Staff (LMTS) – Logic Design
RambusJob Title
Lead Member of Technical Staff (LMTS) – Logic Design
Role Summary
Individual contributor on the Silicon IP (SIP) logic design team focused on micro-architecture and RTL for high-performance memory controllers used in data center and AI applications.
Work closely with verification, physical design, and customer-facing teams to deliver optimized, production-ready RTL blocks.
Experience Level
Senior - typically 8+ years of ASIC/FPGA logic design experience (guidance from posting: 8+ years or equivalent senior experience; 6+ years noted for candidates with advanced degree).
Responsibilities
Primary responsibilities include architecture, RTL design, cross-team collaboration, and customer support.
- Define micro-architecture and implement RTL for schedulers, command pipelines, coherency/ordering logic, and system interfaces.
- Analyze performance, power, and area (PPA) trade-offs and drive data-driven design decisions.
- Collaborate with verification to shape test plans, improve coverage, and debug regression failures; provide RTL fixes when needed.
- Work with physical design to address timing, power, and congestion issues.
- Provide technical support to pre-sales (FAE) and post-sales (AE) customer engagements.
Requirements
Must-have technical skills and experience; separate list for preferred additions.
- Strong SystemVerilog/Verilog RTL design expertise.
- Experience with Questa, Incisive, or VCS simulators.
- Proficiency in scripting (Python, Perl, TCL) for automation and debug.
- Proven ability to learn quickly and work independently across complex projects.
- Solid communication and project management skills; experience collaborating with verification and physical design teams.
- Practical experience analyzing PPA trade-offs and delivering production-quality RTL.
- Customer-facing technical support experience (pre-sales/post-sales) is preferred.
Nice-to-have:
- ASIC synthesis, timing constraints, CDC/RDC experience.
- UVM verification experience.
- Memory subsystem expertise (HBM, LPDDR).
- AMBA AXI or CHI protocol experience.
Education Requirements
Bachelor of Science in Electrical Engineering (BSEE) or Master of Science in Electrical Engineering (MSEE) were specified in the source as common backgrounds; postings also imply equivalent practical experience is acceptable.
About the Company
Rambus develops memory interface chips and Silicon IP for high-performance data center and AI applications. The company offers compensation including base salary, bonus, equity, and benefits.
About the Company
Company: Rambus
Headquarters: Sunnyvale, California, USA
Rambus is a global leader in advanced semiconductor and technology solutions, specializing in enhancing data access and improving performance in computing, networking, and storage applications. The company is known for its innovative IP and solutions in memory, security, and interface technologies. With a strong focus on research and development, Rambus continues to push the boundaries of technology to meet the growing demands of the digital age.
