Lead IC Package Design Engineer

Job Title

Lead IC Package Design Engineer

Role Summary

Experienced IC package design engineer responsible for leading flip‑chip package design and IC–Package–PCB co‑design with emphasis on signal integrity (SI), power integrity (PI), and thermal optimization. Works with cross‑functional teams and customers to deliver high‑performance, cost‑effective package solutions.

Role includes technical leadership, methodology development, and hands‑on validation and simulation work across package and PCB domains.

Experience Level

Senior level — typically 10+ years (10–15 years indicated).

Responsibilities

Primary delivery and leadership responsibilities:

• Lead flip‑chip package design and define bump maps, package stack‑up, and BGA ball maps.
• Drive IC–Package–PCB co‑design, balancing performance, power, cost, technology, and thermal trade‑offs.
• Perform routing feasibility analysis and optimize PCB interfaces for package designs.
• Execute 2D/3D electromagnetic simulations and apply EM and transmission‑line theory to design challenges.
• Extract and analyze S‑parameters and RLGC models to meet SI/PI requirements.
• Validate package and PCB designs in the lab and correlate measurements with simulations.
• Provide program status updates, identify risks, and propose mitigation plans.
• Drive process improvements, develop methodology, and mentor team members while contributing as an individual technical expert.

Requirements

Must‑have technical skills and experience; followed by desirable skills.

• Must-have: Demonstrated expertise in flip‑chip package design with strong SI, PI, and thermal focus.
• Must-have: Hands‑on experience with IC–Package–PCB co‑design and balancing cross‑domain tradeoffs.
• Must-have: Experience performing 2D/3D EM simulations and extracting/analyzing S‑parameters and RLGC models.
• Must-have: Lab validation experience correlating measurements with simulation results.
• Must-have: Experience with Cadence Allegro tools (APD/SIP, PCB Editor) and modeling tools such as Cadence Sigrity PowerSI, ExtractIM, Clarity 3D.
• Must-have: Experience with DRAM and high‑speed memory protocols (examples: DDR4/5, GDDR6/7, HBM3/4, LPDDR5/6).
• Must-have: Proven ability to work independently and in cross‑functional teams; ability to mentor others.
• Nice-to-have: Strong understanding of package cost vs. performance trade‑offs and process/methodology innovation experience.

Education Requirements

BE/BTech or MTech in Electrical or Electronics Engineering, or equivalent practical experience.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.