Lead IC Package Design Engineer

Job Title

Lead IC Package Design Engineer

Role Summary

Experienced IC package design engineer responsible for leading flip‑chip package design and IC–Package–PCB co‑design with emphasis on signal integrity (SI), power integrity (PI), and thermal optimization. The role involves close collaboration with cross‑functional teams and customers to deliver cost‑effective, manufacturable, high‑performance package solutions.

Experience Level

Senior — 10+ years of relevant IC/package design experience (10–15 years indicated).

Responsibilities

Principal responsibilities include:

• Lead flip‑chip package design addressing SI, PI, and thermal constraints.
• Drive IC–Package–PCB co‑design and trade‑off analysis (performance, power, cost, technology, thermal).
• Collaborate with customers and cross‑functional teams to define end‑to‑end solutions.
• Support die floorplanning, IO placement, bump definition, routing feasibility, and package stack‑up optimization.
• Define BGA ball maps and ensure robust PCB design interfaces.
• Perform 2D/3D electromagnetic simulations and apply transmission‑line and EM theory to address design issues.
• Extract and analyze S‑parameters and RLGC models to validate SI/PI targets.
• Validate designs in the lab and correlate measurements with simulation results.
• Provide program status updates, identify risks, and propose mitigation plans.
• Drive process and methodology improvements and mentor junior team members.

Requirements

Must-have skills and experience:

• 10+ years of IC/package design experience with demonstrable work on flip‑chip packages.
• Strong expertise in SI, PI, and thermal analysis for packages and board interfaces.
• Experience with Cadence Allegro tools (APD/SIP, PCB Editor).
• Experience with modeling tools such as Cadence Sigrity PowerSI, ExtractIM, and Clarity 3D.
• Practical experience performing EM simulations and extracting S‑parameters / RLGC models.
• Experience validating designs in lab measurements and correlating to simulation.
• Familiarity with modern DRAM protocols (DDR4/5, GDDR6/7, HBM3/4, LPDDR5/6).
• Proven ability to work independently and within cross‑functional teams; strong communication and reporting skills.
• Demonstrated ability to mentor others and improve design flows or methodologies.

Nice-to-have:

• Deep knowledge of package cost vs. performance trade‑offs and manufacturability considerations.

Education Requirements

BE/BTech or MTech in Electrical or Electronics Engineering, or equivalent relevant education or practical experience.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.