Lead I/O Design Engineer

Job Title

Lead I/O Design Engineer

Role Summary

Design and deliver high-performance I/O IP for advanced SoCs, including GPIO, LVDS, DDR, SerDes support circuits, ESD protection, level shifters, buffers, and termination circuits. Work at transistor level through silicon bring-up to ensure robust, production-ready designs.

Collaborate with system, package, reliability, physical design and product teams; lead technical discussions and guide junior engineers to meet performance, signal integrity, and reliability targets.

Experience Level

Senior-level; typically 5–8 years of experience in Analog/Mixed-Signal or I/O circuit design.

Responsibilities

Accountable for specification, design, verification, and delivery of I/O circuits and supporting IP.

• Design and develop custom I/O circuits: GPIO, LVDS, LVCMOS, SSTL, HSTL, DDR interfaces, and SerDes support circuits.
• Perform transistor-level design and SPICE simulation in advanced CMOS nodes.
• Develop and optimize ESD protection, level shifters, input buffers, output drivers, and on-chip termination.
• Run pre-layout and post-layout simulations for functionality, timing, power, noise, and reliability.
• Perform signal integrity analysis, IBIS model generation, package-aware simulation, crosstalk and reflection analysis.
• Drive layout reviews and collaborate with physical design to meet performance targets and manufacturability checks.
• Support silicon bring-up, lab characterization, debugging, and production ramp activities.
• Produce and maintain design documentation, specifications, and verification reports.

Requirements

Key technical skills and hands-on tools experience required. Degree information is summarized separately below.

• 5–8 years in Analog/Mixed-Signal or I/O circuit design.
• Strong understanding of CMOS device physics and analog circuit fundamentals.
• Deep knowledge of I/O architectures, interface standards, and ESD design methodologies.
• Hands-on experience with Cadence Virtuoso and SPICE-based simulators (Spectre, HSPICE, FineSim).
• Experience with advanced technology nodes (preferred: 16nm / 7nm / 5nm).
• Familiarity with LVS, DRC, EMIR, reliability checks, process corners, Monte Carlo analysis and yield optimization.
• Experience with signal integrity workflows and IBIS model generation.

• Experience with DDR4/DDR5, LPDDR, USB, PCIe, MIPI, Ethernet, SerDes, or related high-speed interfaces.
• Knowledge of package modeling, SI/PI analysis tools and ESD standards (HBM, CDM, IEC).
• Silicon validation and lab characterization experience.
• Scripting skills in Python, Perl, Tcl, or SKILL; familiarity with IBIS-AMI model generation.
• Experience in automotive, AI/ML, networking, mobile, or data center SoCs; exposure to functional safety or reliability requirements.

Education Requirements

Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Microelectronics, or a related technical field.

About the Company

Company: NXP Semiconductors

Headquarters: Nijmegen, Netherlands

NXP Semiconductors N.V. is a global semiconductor company that provides High Performance Mixed Signal and Standard Product solutions. With over 45,000 employees and operations in more than 35 countries, NXP is a leader in secure connectivity solutions for embedded applications, catering to automotive, industrial IoT, mobile, and communication infrastructure markets. The company is committed to innovation and sustainability, advancing a smarter, safer, and more sustainable world through technology.