Lead Engineer – CAD Digital Verification

Job Title

Lead Engineer – CAD Digital Verification

Role Summary

Lead development, enhancement, and support of CAD tools and EDA simulation flows to enable efficient and reliable verification of ASIC/SoC designs. The role focuses on automation, simulation methodologies, and verification infrastructure to improve engineering productivity and design quality.

Join a CAD – Digital Simulation team that supports digital simulation, formal and low-power verification, and collaborates with RTL designers, verification engineers, CAD teams, and EDA vendors.

Experience Level

Senior. See Education Requirements for degree-and-years guidance; technical seniority and leadership expected in CAD/EDA and verification tool development.

Responsibilities

The role requires building and maintaining scalable verification flows, automation, and support processes for simulation and verification activities.

• Develop, deploy, and maintain CAD tools and EDA flows for design verification, formal verification, low-power verification, functional safety, and coverage analysis.
• Collaborate with RTL designers and verification teams to define requirements and solve simulation/verification issues.
• Create and optimize automation scripts to streamline simulation builds, testbench generation, and verification workflows.
• Support RTL simulation, gate-level simulation, and UVM-based verification environments.
• Work with EDA vendors (Cadence, Synopsys, Siemens EDA) to integrate capabilities and resolve tool issues and bottlenecks.
• Assist verification engineers in debugging simulation failures and improving functional and code coverage.
• Develop reusable, scalable CAD methodologies and participate in technical planning and roadmap discussions.

Requirements

Must-have technical skills and capabilities for day-one contribution; degree and years-of-experience details are listed under Education Requirements.

• Proven experience in design verification, CAD/EDA tool development, or verification flow support for ASIC/SoC designs.
• Strong understanding of IP/SoC-level verification methodologies and digital simulation environments.
• Hands-on scripting and programming skills (Python, Perl, Tcl, Bash/shell, Makefiles; C/C++ experience helpful).
• Familiarity with RTL, Verilog/SystemVerilog, and UVM-based verification environments.
• Experience with EDA simulation tools and verification workflows; ability to debug EDA tool issues.
• Comfortable in Linux/UNIX environments and engineering data-management workflows.
• Strong debugging, problem-solving, communication, and cross-functional collaboration skills.

Nice-to-have:

• Experience with Cadence simulation/verification tools and SYSVIP/SYSAPI/SPA.
• Knowledge of low-power verification methodologies (UPF) and gate-level simulation.
• DPI integration experience using C/C++.
• Exposure to formal verification, functional safety, and advanced coverage methodologies.
• Experience developing scalable automation frameworks and improving simulation performance across teams.
• Familiarity with AI-powered tools to enhance productivity and analysis.

Education Requirements

Bachelor's degree in Electrical Engineering, Electronics, Computer Engineering, or a related field (typically paired with 7+ years of relevant industry experience), or a Master’s degree in a related field (typically paired with 5+ years of relevant industry experience).

About the Company

Company: Silicon Labs

Headquarters: Austin, Texas, USA

Silicon Labs is a leading innovator in low-power wireless connectivity, creating embedded technology that connects devices to improve lives. With a focus on advanced edge connectivity applications, the company provides device makers with cutting-edge solutions and support. Headquartered in Austin, Texas, Silicon Labs operates in over 16 countries, serving markets such as smart home, industrial IoT, and smart cities.