Lead Digital Verification Engineer

Job Title

Lead Digital Verification Engineer

Role Summary

Lead verification engineer responsible for verification of digital RTL and development of reusable verification components and environments for high-performance physical IP. Works within a small, multidisciplinary design IP team and coordinates with design, verification, and project management across multiple geographies.

Role expects on-site presence in Montreal, QC, Canada and limited travel (≈5% or less).

Experience Level

Senior (Lead). The posting describes a lead-level role; no explicit years-of-experience requirement is stated.

Responsibilities

Primary duties focus on planning and executing functional verification and delivering reusable verification infrastructure.

• Verify digital RTL modules and implement verification environments.
• Develop reusable verification components and UVM-based testbenches.
• Create and execute test plans; drive functional and code coverage closure.
• Develop and maintain verification flows and metrics-driven verification practices.
• Write and maintain assertions (SystemVerilog Assertions) and directed/constrained tests.
• Collaborate with digital/analog design teams, physical design, production, and project management across locations.
• Report project status and verification progress to technical stakeholders.

Requirements

Key technical skills and experience required or strongly preferred.

• Must-have: Understanding of verification architecture and methodologies, metric-driven verification, UVM principles, SystemVerilog Assertions (SVAs), and digital design flow.
• Must-have: Strong problem-solving and communication skills; ability to work independently and in small teams.
• Nice-to-have: Hands-on experience coding in SystemVerilog UVM.
• Nice-to-have: Experience with scripting languages (Python, Perl, Ruby, sed, awk) for testbench automation.
• Nice-to-have: Exposure to protocols such as PCIe, USB, SATA, Ethernet, DisplayPort, HDMI.
• Nice-to-have: Exposure to formal verification, mixed-signal verification, Cadence tools, or low-power verification using CPF/UPF.

Education Requirements

Minimum: Bachelor of Science in Electrical Engineering, Computer Engineering, Computer Science, or related field. Preferred: Master of Science in EE/CPE/CS. (Degrees listed in source: BSc required; MSc preferred.)

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.