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Lead Digital Verification Engineer

Cadence Design Systems
August 31, 2026
Full-time
On-site
Montreal, Quebec, Canada
$89,600 - $166,400 CAD yearly
Verification Jobs, Level - Senior

Job Title

Lead Digital Verification Engineer

Role Summary

Lead verification of digital RTL for high-performance physical IP used with industry-standard protocols. Develop reusable verification components and environments, drive verification flows and metrics, and coordinate with design and project teams across locations.

Experience Level

Senior / Lead level. The posting expects an experienced verification engineer; exact years of experience not specified.

Responsibilities

Primary responsibilities include:

  • Plan and execute verification of digital RTL and associated verification environments.
  • Develop reusable verification components, test plans, metrics, and automation.
  • Create and close functional coverage and code coverage; implement SystemVerilog assertions as needed.
  • Drive verification flow development and metric-driven verification processes.
  • Collaborate with digital/analog design teams, verification teams, and project management across geographies.
  • Report development status and resolve verification issues to meet project timelines and quality targets.
  • Mentor and guide other engineers as required.

Requirements

Must-have and preferred skills:

  • Understanding of verification architecture and methodologies, including metric-driven approaches and UVM concepts.
  • Knowledge of SystemVerilog Assertions (SVA) and digital design flow.
  • Experience with functional and code coverage closure and test-plan-driven verification.
  • Familiarity with scripting languages for automation (Python, Perl, Ruby, sed, awk).
  • Ability to work independently, communicate effectively, and collaborate with distributed teams; English proficiency required.
  • Willingness to work onsite in Montreal and travel approximately 5% or less.
  • Preferred: hands-on SystemVerilog UVM coding, experience with formal verification, mixed-signal verification exposure, Cadence tool experience, and low-power verification using CPF or UPF.

Education Requirements

Posting specifies a Bachelor of Science in Electrical Engineering, Computer Engineering, or Computer Science as a minimum; a Master of Science in a related field is preferred. The posting implies equivalent practical experience may be considered.


About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.

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Date Posted: 2026-08-29