Lead Design Verification Engineer

Job Title

Lead Design Verification Engineer

Role Summary

Technical lead responsible for defining and executing end-to-end verification strategy for chassis and interconnect IP programs from planning through signoff. The role partners with architecture, design, software, and methodology teams to resolve cross-team issues and drive predictable, high-quality silicon delivery.

Experience Level

Senior-level. Role expects 14+ years of relevant design verification experience.

Responsibilities

Primary responsibilities include verification strategy, technical leadership, and delivery ownership across multiple IPs and subsystem integration.

• Define verification strategy, technical standards, and execution model for critical blocks and scale delivery from IP to subsystem.
• Lead development of reusable environments, complex testbenches, checkers, VIPs, and behavioral models.
• Collaborate with architecture, design, software, and methodology from specification through bring-up; unblock cross-discipline issues.
• Take ownership of functional signoff and achievement of performance and power targets for multiple critical blocks.
• Balance requirements, schedules, and resources while delivering IP to multiple internal customers.
• Drive unified verification approaches combining simulation, formal, and emulation; evaluate and adopt emerging methodologies including ML-assisted flows.
• Mentor and develop senior and junior verification engineers and establish verification best practices.

Requirements

Strong, hands-on verification expertise and proven leadership delivering complex IP and subsystem verification.

• Must-have: 14+ years of relevant design verification experience with substantial IP DV and subsystem/SoC verification ownership.
• Must-have: Deep expertise in interconnects, caches, and memory subsystems and experience with protocols such as AMBA CHI, ACE, AXI, PCIe, UCIe, and CXL.
• Must-have: Experience with global functions (debug, trace, clock/power management, RAS, QoS, security).
• Must-have: Strong background in simulation and formal methodologies (UVM, SVA, ABV) and multi-engine strategies that include emulation and co-simulation.
• Must-have: Advanced hands-on coding in SystemVerilog/UVM, C/C++, and Python; experience with build systems and delivering configurable, reusable verification collateral.
• Must-have: Working familiarity with RTL, physical design constraints, and CAD tool flows sufficient to review and contribute outside core DV tasks.
• Nice-to-have: Hands-on experience with formal tools (JasperGold, VC Formal) and emulation/FPGA-based verification and combining engines for unified bug closure.
• Nice-to-have: Prior work with system IPs such as MMUs (SMMU/IOMMU), interrupt controllers, and related software stacks.
• Other: Strong communication and organizational skills; experience establishing technical standards and delivering silicon to schedule.

Education Requirements

BS or MS in Electrical Engineering, Computer Science, or a related technical field (as stated). If no degree, equivalent technical experience is commonly considered.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.