Lead Design Verification Application Engineer

Job Title

Lead Design Verification Application Engineer

Role Summary

Customer-facing application engineer on the North America Verification Field Applications Engineering team. Deploy and support Cadence verification platforms (including Xcelium and Verisium AI/ML tools) in pre- and post-sales engagements, develop customer-specific verification components and methodologies, and collaborate with R&D and product teams to deliver solutions that secure design wins.

Primary mission: ensure customer success by providing technical leadership, demonstrating tools, and enabling advanced verification flows.

Experience Level

Senior — the role expects demonstrated leadership in verification. Posting specifies a minimum of 3+ years of hands-on experience with HDLs and verification flows.

Responsibilities

Core responsibilities include technical customer engagement, solution development, and collaboration with R&D and product teams.

• Serve as the primary technical contact for customers during evaluations and deployments.
• Provide front-line pre- and post-sales technical support for verification platforms.
• Develop customer-specific verification requirements, advanced verification components, and methodology support.
• Support technical evaluations, benchmark development, and performance analysis for tools such as Xcelium and Verisium.
• Create and deliver technical presentations, demonstrations, and application-focused literature (application notes, technical articles).
• Collaborate with R&D and marketing to design competitive technical solutions that address customer needs.
• Champion customer requirements internally and own customer success for assigned accounts/projects.

Requirements

Must-have technical skills, tools experience, and professional competencies.

• 3+ years practical experience with SystemVerilog, VHDL, and Verilog.
• Strong understanding of object-oriented programming and experience in one or more languages such as C++, Java, Python, or SystemVerilog.
• Proficiency with Linux/Unix environments and scripting (Perl, Tcl, Python, or similar).
• Excellent verbal and written communication skills; able to present technical content to customers and internal teams.
• Self-motivated, effective team player, and strong problem-solving skills.

Preferred:

• Experience with simulation, functional verification, testbench creation, and debug.
• Experience with C/C++ or SystemC and verification environments.
• Knowledge of digital design fundamentals: architecture, micro-architecture, synthesis, and timing.
• Background in digital design or digital verification methodologies.

Education Requirements

BS, MS, or PhD in Computer Science, Computer Engineering, Electrical Engineering, or a related technical field.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.