Lead Design Engineer (Virtual Solution)

Job Title

Lead Design Engineer (Virtual Solution)

Role Summary

Design and deliver system-level AVIP solutions for emulation and prototyping platforms (Palladium, Protium). Lead integration of Accelerated Verification IP and end-to-end verification flows to validate complex SoCs and subsystems.

Collaborate with product engineering, applications engineering, and customers to enable bring-up, debug, and deployment while optimizing for performance, scalability, and emulation efficiency.

Experience Level

Senior — the posting specifies at least 3 years of relevant experience and expects senior-level technical ownership.

Responsibilities

Primary responsibilities include:

• Design and implement system-level AVIP solutions for emulation/prototyping platforms.
• Build and integrate Accelerated Verification IP environments for SoC and subsystem validation.
• Develop end-to-end verification flows: AVIP integration, testbench and system modeling, and bare-metal/driver-level validation.
• Optimize solutions for performance, scalability, and emulation efficiency.
• Create custom test cases, tools, and automation for embedded, co-emulation, and hybrid flows.
• Work with cross-functional teams and customers to debug and resolve system-level issues.
• Support customer enablement during bring-up, debug, and solution deployment.

Requirements

Must-have technical skills and experience:

• At least 3 years of relevant industry experience.
• RTL design experience in SystemVerilog / Verilog.
• C/C++ development experience for modeling, testbench, or system integration.
• Expertise in at least one high-speed protocol such as PCIe, CXL, AMBA, UCIe, or Ethernet.
• Strong debugging skills for complex system integration issues.
• Excellent English communication skills (verbal and written).

Nice-to-have:

• Hands-on experience with Palladium, Protium, FPGA, or other emulation/prototyping platforms.
• Experience with AVIP, UVM, Qemu/Gem5, and multi-language environments (SystemVerilog + C/C++ + Python).
• Experience with end-to-end validation flows (simulation → emulation → prototyping).
• Exposure to AI/ML techniques applied to verification or tooling.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field (explicitly stated). The posting also specifies at least 3 years of relevant experience.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.