Lead Design Engineer - Verification

Job Title

Lead Design Engineer - Verification

Role Summary

Senior verification engineer on the IP verification team responsible for verification of high-performance PHY IPs (e.g., eUSB2v2, USB4-PHY, PCIe, eDP/DP, SATA). Works across block, PHY-top and controller+PHY subsystem levels to deliver signoff-quality IP to customers.

Experience Level

Senior. The posting requests 3+ years of industry digital/ASIC verification experience.

Responsibilities

Primary duties include verification architecture, planning, implementation, and delivery for serial-interface PHY IPs.

• Design and maintain UVM/SystemVerilog verification environments: testbench architecture, agents/UVCs, sequences, scoreboards, register models (UVM RAL) and checkers.
• Create verification plans from protocol specs and design docs; define functional coverage, SVA assertions, corner/error injection strategies; drive coverage closure and signoff metrics.
• Run and maintain regression suites on simulation/regression platforms (e.g., Xcelium, vManager); triage failures and debug RTL/testbench using waveform tools.
• Apply low-power verification, CDC/RDC checks, X-propagation, gate-level simulation and formal techniques as appropriate.
• Integrate/configure commercial VIP for serial protocols and verify firmware/hardware interaction and bring-up flows with firmware and design teams.
• Collaborate with design, lab, and project management teams worldwide to support testability, lab bring-up and pre/post-silicon debug.
• Contribute to verification infrastructure, methodology and QA for customer releases.

Requirements

Must-have technical skills and experience, followed by preferred additions.

• Must-have: 3+ years industry experience in digital/ASIC verification.
• Must-have: Hands-on SystemVerilog and UVM experience; constrained-random verification, functional coverage and assertion-based verification.
• Must-have: Knowledge of one or more serial protocol standards (USB, DP, PCIe, Ethernet, etc.) including link training, power management and protocol layering.
• Must-have: Experience with verification planning and coverage-driven signoff.
• Must-have: Basic understanding of analog/mixed-signal verification and system-level view of physical-interface IPs.
• Must-have: Strong cross-functional communication skills in English and Mandarin; self-starter, motivated, collaborative.
• Preferred: Direct verification experience of high-speed serial interface link IPs (PHY/PCS/controller) in advanced nodes.
• Preferred: Experience with Cadence tools (Xcelium, vManager, Verisium, JasperGold, Palladium) and with low-power verification (UPF/CPF), gate-level sim, mixed-signal co-sim.
• Preferred: Scripting/automation skills (Python, Perl, Tcl) and experience with controller+PHY subsystem-level verification; interest in AI-assisted verification.

Education Requirements

MS or BS in Electrical Engineering, Computer Engineering, or a related technical field (MS/BS explicitly listed in the posting).

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.