Lead Design Engineer - Verification
Work as a hands-on VLSI design verification engineer on SoC and IP verification for customer projects. Collaborate with local design teams and global stakeholders to define verification strategy, execute verification plans, and close coverage and regression goals.
Contribute to verification methodology and reusable environments to ensure timely, high-quality delivery.
Senior-level (Lead). The posting specifies 3–5 years of hands-on VLSI/SOC design verification experience.
Primary responsibilities include planning and executing verification for SoC and IP, debugging complex issues, and coordinating with customers and internal teams.
Must-have technical skills are listed below; preferred items are indicated.
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field (the posting specifies Bachelor’s or Master’s).
Company: Cadence Design Systems
Headquarters: San Jose, California, USA
Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.
