Lead Design Engineer (Synthesis/LEC/CLP)
Cadence Design SystemsJob Title
Lead Design Engineer (Synthesis/LEC/CLP)
Role Summary
The Lead Design Engineer will execute synthesis, LEC and CLP sign-off flows and contribute to low-power (UPF) closure for advanced ASIC/SoC blocks. This is a hands-on execution role focused on debugging synthesis and LEC issues, improving quality of results, and owning closure activities for assigned blocks.
Works closely with RTL, PD, and DFT teams to resolve cross-functional issues and prepare technical status summaries.
Experience Level
Senior - 5–8 years of relevant ASIC/SoC implementation experience.
Responsibilities
Primary responsibilities include synthesis, equivalence checking, constraint/ECO work, and cross-team debugging to achieve closure.
- Run and debug LEC sign-off for design blocks; investigate and resolve NEQs and constraint mismatches.
- Execute and optimize Genus synthesis runs to improve QoR and resolve SDC/constraint issues.
- Support CLP flows and contribute to CLP sign-off activities.
- Write and maintain ECO scripts and timing/power constraints for assigned blocks.
- Independently triage and document issues; escalate complex or systemic problems as needed.
- Collaborate with PD, DFT, and RTL teams to resolve cross-functional issues affecting synthesis/LEC/CLP closure.
- Prepare clear status updates and concise technical summaries for internal tracking.
Requirements
Must-have technical skills and experience for the role.
- 5–8 years of hands-on experience in ASIC synthesis, LEC, and low-power verification flows.
- Working knowledge of Cadence Genus and Conformal (LEC and/or CLP).
- Familiarity with UPF/CPF-based power intent concepts (IEEE 1801).
- Scripting proficiency in Tcl, Perl, or Python and comfort working in Unix/Linux environments.
- Solid understanding of digital design fundamentals, STA basics, and low-power architecture concepts.
- Strong verbal and written communication skills and ability to work independently on assigned blocks.
Education Requirements
BE/BTech or ME/MS/MTech in Electrical, Electronics, or related discipline; OR equivalent practical experience in ASIC/SoC implementation and verification.
About the Company
Company: Cadence Design Systems
Headquarters: San Jose, California, USA
Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.
