Lead Design Engineer

Job Title

Lead Design Engineer — Analog Mixed-Signal (SerDes)

Role Summary

The Lead Design Engineer will define and implement silicon-ready analog/mixed-signal circuit architectures for high-speed SerDes transceivers targeting data-center, networking, AI, and HPC applications. The role partners with architecture, digital, layout, verification, signal-integrity, and post-silicon teams to deliver tapeout-ready IP and production releases.

Experience Level

Senior. The posting indicates experience expectations of 3+ years with a B.S. or 1+ years with an M.S. in a relevant field.

Responsibilities

Deliver and validate high-speed SerDes IP from specification through silicon bring-up and production release.

• Design and verify SerDes blocks: TX drivers, serializers, RX front ends, CTLEs, samplers, comparators, ADCs/DACs, PLLs/DLLs, clock dividers, distribution networks, regulators, bias circuits, and calibration loops.
• Translate link-level requirements into circuit specifications and optimize performance across PVT, mismatch, aging, and extracted parasitics.
• Develop behavioral models and support mixed-signal and top-level verification flows.
• Collaborate with layout and signal-integrity teams on physical implementation and post-layout signoff.
• Support tapeout, silicon bring-up, lab characterization, debug, and production release activities.
• Document results and present technical design reviews.

Requirements

Core technical skills and hands-on tool experience required; preferred items listed separately.

Must-have:

• Strong analog CMOS fundamentals: noise, jitter, feedback, signal integrity, and data-converter concepts.
• Hands-on transistor-level design experience with high-speed SerDes circuits (TX/RX, equalization, clocking, calibration).
• Proficiency with Cadence Virtuoso, Spectre/SpectreRF, ADE, parasitic extraction, and mixed-signal verification flows.
• Ability to develop behavioral/functional models and support mixed-signal verification.
• Strong analytical skills, engineering judgment, and effective communication and collaboration.

Nice-to-have:

• Experience with PAM4/NRZ SerDes, Ethernet/PCIe/CXL standards, and FinFET or advanced CMOS processes.
• Familiarity with MATLAB or C for architecture work; SystemVerilog/Verilog-A for modeling; Perl or Python for automation.
• Experience with lab characterization, custom analog layout, and taking mixed-signal IP from architecture through tapeout and silicon validation.
• Experience using AI-assisted engineering tools responsibly for design exploration and workflow automation.

Education Requirements

Required: B.S. in Electrical Engineering or a related field with 3+ years of relevant experience, or an M.S. in a related field with 1+ years of relevant experience. (Degrees and years are taken from the posting.)

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.