Lead Design Engineer

Job Title

Lead Design Engineer

Role Summary

Senior frontend design engineer responsible for architecture, micro-architecture and RTL implementation of high-performance physical IP used in SoC and IP subsystems.

Work on advanced physical IP (consumer PHYs and serial interfaces) within a cross-functional team in Nanjing, coordinating with verification, analog, layout, backend, firmware, lab validation, and global delivery teams; provide pre- and post-silicon customer support.

Experience Level

Senior - 5+ years of relevant industry experience; 3+ years in an ASIC design role delivering advanced IP or ASIC/SoC products.

Responsibilities

Key responsibilities include architecture-to-RTL delivery, verification planning, cross-functional integration, and support for validation and customer releases.

• Lead frontend design for high-performance physical IP (examples: eUSB2v2, USB4-PHY, PCIe, ONFI, eDP/DP, SATA).
• Drive architecture, micro-architecture and RTL implementation; refine features and requirements through the design lifecycle.
• Develop synthesis constraints, power-management strategies and DFT implementation guidance.
• Implement and verify low-power features (power islands, state retention, isolation).
• Define verification requirements: coverage points, test strategy, corner conditions, stimulus and FPGA/Palladium testing plans.
• Coordinate with project management and cross-functional teams (Analog, Layout, Backend, Firmware, Lab Bring-up, Pre/Post-Silicon) to deliver IP on schedule and to quality standards.
• Integrate IP into subsystems and support QA and release activities for customer deliveries.
• Provide pre- and post-silicon application support to global customers as needed.

Requirements

Must-have technical skills and experience; concise list of required qualifications followed by nice-to-have items.

• 5+ years of relevant industry experience; 3+ years in an ASIC design role delivering IP or SoC products.
• Deep knowledge of design architecture, RTL design/verification and end-to-end ASIC methodology.
• Experience with synthesis, constraint generation, power management and DFT.
• Understanding of low-power design techniques (power islands, retention, isolation).
• Familiarity with one or more serial interface standards (USB, PCIe, DisplayPort, Ethernet, SATA, etc.).
• Understanding of analog mixed-signal concepts, SI/PI, post-silicon validation and system-level behavior of physical interface IPs.
• Strong cross-functional communication skills in English and Mandarin.
• Self-starter able to work independently and collaboratively across geographies.

Nice-to-have:

• Direct experience with high-speed serial link IPs in advanced process nodes.
• Experience with SystemVerilog, Python, C/C++ and scripting for design/verification flows.
• Knowledge of embedded microcontroller/DSP usage and firmware interaction.
• Familiarity with Cadence ASIC design tools and flows.

Education Requirements

MS or BS in Electrical Engineering, Computer Engineering, or a related field (MS / BS in Electrical/Computer Engineering or related degree as stated).

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.