Lead Design Engineer
Work on physical design and timing closure for high-capacity, hardware-assisted verification platforms (Palladium and Protium) and associated SoCs. The role focuses on RTL synthesis, floorplanning, clock tree synthesis, timing closure, IR drop analysis, physical verification, and tape-out documentation.
Collaborate with front-end RTL designers and back-end verification teams to deliver tape-out ready designs on advanced process nodes.
Senior. Typical background: experienced physical design engineer. Cadence specifies degree-based minimums (see Education Requirements); equivalent industry experience may apply.
Primary responsibilities include implementation, verification, timing closure and preparing designs for tape-out.
Must-have technical skills and experience.
Nice-to-have: direct experience with Palladium/Protium hardware-assisted verification platforms and large-capacity emulation flows.
Cadence specifies: BS in Electrical Engineering with a minimum of 5 years of relevant experience, or MS with a minimum of 3 years of relevant experience. (No other degrees or equivalent-experience language provided.)
Company: Cadence Design Systems
Headquarters: San Jose, California, USA
Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.
